bindings/clock/qcom%2Cqca8k-nsscc.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,qca8k-nsscc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm NSS Clock & Reset Controller on QCA8386/QCA8084
10   - Bjorn Andersson <andersson@kernel.org>
11   - Luo Jie <quic_luoj@quicinc.com>
15   on QCA8386(switch mode)/QCA8084(PHY mode)
18     include/dt-bindings/clock/qcom,qca8k-nsscc.h
19     include/dt-bindings/reset/qcom,qca8k-nsscc.h
24       - const: qcom,qca8084-nsscc
25       - items:
26           - enum:
27               - qcom,qca8082-nsscc
28               - qcom,qca8085-nsscc
29               - qcom,qca8384-nsscc
30               - qcom,qca8385-nsscc
31               - qcom,qca8386-nsscc
32           - const: qcom,qca8084-nsscc
36       - description: Chip reference clock source
37       - description: UNIPHY0 RX 312P5M/125M clock source
38       - description: UNIPHY0 TX 312P5M/125M clock source
39       - description: UNIPHY1 RX 312P5M/125M clock source
40       - description: UNIPHY1 TX 312P5M/125M clock source
41       - description: UNIPHY1 RX 312P5M clock source
42       - description: UNIPHY1 TX 312P5M clock source
46       - description: MDIO bus address for Clock & Reset Controller register
48   reset-gpios:
53   - compatible
54   - clocks
55   - reg
56   - reset-gpios
59   - $ref: qcom,gcc.yaml#
64   - |
65     #include <dt-bindings/gpio/gpio.h>
67       #address-cells = <1>;
68       #size-cells = <0>;
70       clock-controller@18 {
71         compatible = "qcom,qca8084-nsscc";
73         reset-gpios = <&tlmm 51 GPIO_ACTIVE_LOW>;
81         #clock-cells = <1>;
82         #reset-cells = <1>;
83         #power-domain-cells = <1>;