bindings/clock/qcom%2Cgcc-qcs404.yaml

1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-qcs404.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on QCS404
10   - Stephen Boyd <sboyd@kernel.org>
11   - Taniya Das <quic_tdas@quicinc.com>
15   domains on QCS404.
17   See also:: include/dt-bindings/clock/qcom,gcc-qcs404.h
21     const: qcom,gcc-qcs404
25       - description: XO source
26       - description: Sleep clock source
27       - description: PCIe 0 PIPE clock (optional)
28       - description: DSI phy instance 0 dsi clock
29       - description: DSI phy instance 0 byte clock
30       - description: HDMI phy PLL clock
32   clock-names:
34       - const: cxo
35       - const: sleep_clk
36       - const: pcie_0_pipe_clk_src
37       - const: dsi0pll
38       - const: dsi0pllbyte
39       - const: hdmi_pll
42   - compatible
43   - '#power-domain-cells'
46   - $ref: qcom,gcc.yaml#
51   - |
52     clock-controller@1800000 {
53       compatible = "qcom,gcc-qcs404";
55       #clock-cells = <1>;
56       #reset-cells = <1>;
57       #power-domain-cells = <1>;