bindings/clock/mvebu-gated-clock.txt

12 -----------------------------------
21 17	sdio	SDHCI Host
29 -----------------------------------
35 8	audio		Audio Cntrl
40 17	sdio		SDHCI Host
56 -----------------------------------
64 8	pex0		PCIe 0
83 -----------------------------------
87 8	pex0		PCIe 0
97 -----------------------------------
106 8	pex3	PCIe Cntrl 3
111 17	sdio	SDHCI Host
124 -----------------------------------
128 17	sdio	SDHCI Host
134 -----------------------------------
141 8	sdio0	SDHCI Host 0
142 9	sdio1	SDHCI Host 1
157 -----------------------------------
165 8	xor0	XOR DMA 0
176 - compatible : shall be one of the following:
177 	"marvell,armada-370-gating-clock" - for Armada 370 SoC clock gating
178 	"marvell,armada-375-gating-clock" - for Armada 375 SoC clock gating
179 	"marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating
180 	"marvell,armada-390-gating-clock" - for Armada 39x SoC clock gating
181 	"marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating
182 	"marvell,mv98dx3236-gating-clock" - for 98dx3236 SoC clock gating
183 	"marvell,dove-gating-clock" - for Dove SoC clock gating
184 	"marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating
185 - reg : shall be the register address of the Clock Gating Control register
186 - #clock-cells : from common clock binding; shall be set to 1
189 - clocks : default parent clock phandle (e.g. tclk)
193 gate_clk: clock-gating-control@d0038 {
194 	compatible = "marvell,dove-gating-clock";
198 	#clock-cells = <1>;
202 	compatible = "marvell,dove-sdhci";
203 	/* get clk gate bit 8 (sdio0) */
204 	clocks = <&gate_clk 8>;