bindings/clock/mvebu-gated-clock.txt

12 -----------------------------------
14 1	pex0_en	PCIe 0 Clock out
15 2	pex1_en	PCIe 1 Clock out
18 5	pex0	PCIe Cntrl 0
19 9	pex1	PCIe Cntrl 1
29 -----------------------------------
33 5	pex0		PCIe 0 Clock out
34 6	pex1		PCIe 1 Clock out
56 -----------------------------------
61 5	pex1		PCIe 1
62 6	pex2		PCIe 2
63 7	pex3		PCIe 3
64 8	pex0		PCIe 0
83 -----------------------------------
84 5	pex1		PCIe 1
85 6	pex2		PCIe 2
86 7	pex3		PCIe 3
87 8	pex0		PCIe 0
97 -----------------------------------
103 5	pex0	PCIe Cntrl 0
104 6	pex1	PCIe Cntrl 1
105 7	pex2	PCIe Cntrl 2
106 8	pex3	PCIe Cntrl 3
124 -----------------------------------
127 5	pex0	PCIe Cntrl 0
134 -----------------------------------
139 4	pex0	PCIe Cntrl 0
140 5	pex1	PCIe Cntrl 1
157 -----------------------------------
159 2	pex0	PCIe Cntrl 0
163 6	dunit	SDRAM Cntrl
171 18	pex1	PCIe Cntrl 1
176 - compatible : shall be one of the following:
177 	"marvell,armada-370-gating-clock" - for Armada 370 SoC clock gating
178 	"marvell,armada-375-gating-clock" - for Armada 375 SoC clock gating
179 	"marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating
180 	"marvell,armada-390-gating-clock" - for Armada 39x SoC clock gating
181 	"marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating
182 	"marvell,mv98dx3236-gating-clock" - for 98dx3236 SoC clock gating
183 	"marvell,dove-gating-clock" - for Dove SoC clock gating
184 	"marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating
185 - reg : shall be the register address of the Clock Gating Control register
186 - #clock-cells : from common clock binding; shall be set to 1
189 - clocks : default parent clock phandle (e.g. tclk)
193 gate_clk: clock-gating-control@d0038 {
194 	compatible = "marvell,dove-gating-clock";
198 	#clock-cells = <1>;
202 	compatible = "marvell,dove-sdhci";