Lines Matching +full:host +full:- +full:id

5 should specify the desired clock by having the clock ID in its
6 "clocks" phandle cell. The clock ID is directly mapped to the
11 ID Clock Peripheral
12 -----------------------------------
20 15 sata0 SATA Host 0
21 17 sdio SDHCI Host
25 30 sata1 SATA Host 0
28 ID Clock Peripheral
29 -----------------------------------
39 16 usb3 USB3 Host
40 17 sdio SDHCI Host
41 18 usb USB Host
55 ID Clock Peripheral
56 -----------------------------------
65 9 usb3h0 USB3 Host 0
66 10 usb3h1 USB3 Host 1
82 ID Clock Peripheral
83 -----------------------------------
88 9 usb3h0 USB3 Host 0
89 10 usb3h1 USB3 Host 1
96 ID Clock Peripheral
97 -----------------------------------
109 15 sata0 SATA Host 0
111 17 sdio SDHCI Host
112 18 usb0 USB Host 0
113 19 usb1 USB Host 1
114 20 usb2 USB Host 2
120 30 sata1 SATA Host 1
123 ID Clock Peripheral
124 -----------------------------------
128 17 sdio SDHCI Host
129 18 usb0 USB Host 0
133 ID Clock Peripheral
134 -----------------------------------
135 0 usb0 USB Host 0
136 1 usb1 USB Host 1
138 3 sata SATA Host
141 8 sdio0 SDHCI Host 0
142 9 sdio1 SDHCI Host 1
156 ID Clock Peripheral
157 -----------------------------------
160 3 usb0 USB Host 0
167 14 sata0 SATA Host 0
168 15 sata1 SATA Host 1
176 - compatible : shall be one of the following:
177 "marvell,armada-370-gating-clock" - for Armada 370 SoC clock gating
178 "marvell,armada-375-gating-clock" - for Armada 375 SoC clock gating
179 "marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating
180 "marvell,armada-390-gating-clock" - for Armada 39x SoC clock gating
181 "marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating
182 "marvell,mv98dx3236-gating-clock" - for 98dx3236 SoC clock gating
183 "marvell,dove-gating-clock" - for Dove SoC clock gating
184 "marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating
185 - reg : shall be the register address of the Clock Gating Control register
186 - #clock-cells : from common clock binding; shall be set to 1
189 - clocks : default parent clock phandle (e.g. tclk)
193 gate_clk: clock-gating-control@d0038 {
194 compatible = "marvell,dove-gating-clock";
198 #clock-cells = <1>;
202 compatible = "marvell,dove-sdhci";