bindings/clock/mvebu-gated-clock.txt

12 -----------------------------------
16 3	ge1	Gigabit Ethernet 1
17 4	ge0	Gigabit Ethernet 0
29 -----------------------------------
42 19	gop		Gigabit Ethernet MAC
56 -----------------------------------
58 2	ge2		Gigabit Ethernet 2
59 3	ge1		Gigabit Ethernet 1
60 4	ge0		Gigabit Ethernet 0
66 10	usb3h1		USB3 Host 1
83 -----------------------------------
89 10	usb3h1		USB3 Host 1
97 -----------------------------------
99 1	ge3	Gigabit Ethernet 3
100 2	ge2	Gigabit Ethernet 2
101 3	ge1	Gigabit Ethernet 1
102 4	ge0	Gigabit Ethernet 0
124 -----------------------------------
125 3	ge1	Gigabit Ethernet 1
126 4	ge0	Gigabit Ethernet 0
134 -----------------------------------
137 2	ge	Gigabit Ethernet
143 10	nand	NAND Cntrl
152 30	gephy	Gigabit Ethernel PHY
157 -----------------------------------
158 0	ge0	Gigabit Ethernet 0
172 19	ge1	Gigabit Ethernet 1
176 - compatible : shall be one of the following:
177 	"marvell,armada-370-gating-clock" - for Armada 370 SoC clock gating
178 	"marvell,armada-375-gating-clock" - for Armada 375 SoC clock gating
179 	"marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating
180 	"marvell,armada-390-gating-clock" - for Armada 39x SoC clock gating
181 	"marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating
182 	"marvell,mv98dx3236-gating-clock" - for 98dx3236 SoC clock gating
183 	"marvell,dove-gating-clock" - for Dove SoC clock gating
184 	"marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating
185 - reg : shall be the register address of the Clock Gating Control register
186 - #clock-cells : from common clock binding; shall be set to 1
189 - clocks : default parent clock phandle (e.g. tclk)
193 gate_clk: clock-gating-control@d0038 {
194 	compatible = "marvell,dove-gating-clock";
198 	#clock-cells = <1>;
202 	compatible = "marvell,dove-sdhci";