bindings/clock/mediatek%2Cmt8188-sys-clock.yaml

1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt8188-sys-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek System Clock Controller for MT8188
10   - Garmin Chang <garmin.chang@mediatek.com>
14   PLLs -->
15           dividers -->
17                            -->
21   The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
29       - enum:
30           - mediatek,mt8188-apmixedsys
31           - mediatek,mt8188-infracfg-ao
32           - mediatek,mt8188-pericfg-ao
33           - mediatek,mt8188-topckgen
34       - const: syscon
39   '#clock-cells':
42   '#reset-cells':
46   - compatible
47   - reg
48   - '#clock-cells'
53   - |
54     clock-controller@10000000 {
55         compatible = "mediatek,mt8188-topckgen", "syscon";
57         #clock-cells = <1>;