Lines Matching full:scg1
24 A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
95 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
96 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
97 <&scg1 IMX7ULP_CLK_DDR_DIV>,
98 <&scg1 IMX7ULP_CLK_APLL_PFD2>,
99 <&scg1 IMX7ULP_CLK_APLL_PFD1>,
100 <&scg1 IMX7ULP_CLK_APLL_PFD0>,
101 <&scg1 IMX7ULP_CLK_UPLL>,
102 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
103 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
104 <&scg1 IMX7ULP_CLK_ROSC>,
105 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;