Lines Matching full:cmu_top
19 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
20 dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
88 - description: HSI0 bus clock (from CMU_TOP)
89 - description: DPGTC (from CMU_TOP)
90 - description: USB DRD controller clock (from CMU_TOP)
91 - description: USB Display Port debug clock (from CMU_TOP)
113 - description: High Speed Interface bus clock (from CMU_TOP)
114 - description: High Speed Interface pcie clock (from CMU_TOP)
115 - description: High Speed Interface ufs clock (from CMU_TOP)
116 - description: High Speed Interface mmc clock (from CMU_TOP)
136 - description: Misc bus clock (from CMU_TOP)
137 - description: Misc sss clock (from CMU_TOP)
157 - description: Connectivity Peripheral 0/1 bus clock (from CMU_TOP)
158 - description: Connectivity Peripheral 0/1 IP clock (from CMU_TOP)
169 # Clock controller node for CMU_TOP
173 cmu_top: clock-controller@1e080000 {