bindings/bus/st%2Cstm32mp25-rifsc.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/st,stm32mp25-rifsc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Gatien Chevallier <gatien.chevallier@foss.st.com>
19     - RISC registers associated with RISUP logic (resource isolation device unit
20       for peripherals), assign all non-RIF aware peripherals to zero, one or
22     - RIMC registers: associated with RIMU logic (resource isolation master
23       unit), assign all non RIF-aware bus master to one security domain by
28     - RISC registers associated with RISAL logic (resource isolation device unit
29       for address space - Lite version), assign address space subregions to one
36         const: st,stm32mp25-rifsc
38     - compatible
43       - const: st,stm32mp25-rifsc
44       - const: simple-bus
49   "#address-cells":
52   "#size-cells":
57   "#access-controller-cells":
63   "^.*@[0-9a-f]+$":
70       - access-controllers
73   - compatible
74   - reg
75   - "#address-cells"
76   - "#size-cells"
77   - "#access-controller-cells"
78   - ranges
83   - |
88     #include <dt-bindings/interrupt-controller/arm-gic.h>
91         compatible = "st,stm32mp25-rifsc", "simple-bus";
93         #address-cells = <1>;
94         #size-cells = <1>;
95         #access-controller-cells = <1>;
99               compatible = "st,stm32h7-uart";
103               access-controllers = <&rifsc 32>;