bindings/bus/socionext%2Cuniphier-system-bus.yaml

1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/bus/socionext,uniphier-system-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UniPhier System Bus
10   The UniPhier System Bus is an external bus that connects on-board devices to
11   the UniPhier SoC. It is a simple (semi-)parallel bus with address, data, and
12   some control signals. It supports up to 8 banks (chip selects).
16   within each bank to the CPU-viewed address. The needed setup includes the
21   - Masahiro Yamada <yamada.masahiro@socionext.com>
25     const: socionext,uniphier-system-bus
30   "#address-cells":
32       The first cell is the bank number (chip select).
36   "#size-cells":
41       Provide address translation from the System Bus to the parent bus.
44       The address region(s) that can be assigned for the System Bus is
45       implementation defined. Some SoCs can use 0x00000000-0x0fffffff and
46       0x40000000-0x4fffffff, while other SoCs only 0x40000000-0x4fffffff.
47       There might be additional limitations depending on SoCs and the boot mode.
53         bank 0 to 0x42000000-0x43ffffff, bank 5 to 0x46000000-0x46ffffff
55         bank 0 to 0x48000000-0x49ffffff, bank 5 to 0x44000000-0x44ffffff
61   "^.*@[1-5],[1-9a-f][0-9a-f]+$":
62     description: Devices attached to chip selects
66   - compatible
67   - reg
68   - "#address-cells"
69   - "#size-cells"
70   - ranges
75   - |
77     // - the Ethernet device is connected at the offset 0x01f00000 of CS1 and
79     // - the UART device is connected at the offset 0x00200000 of CS5 and
82     system-bus@58c00000 {
83         compatible = "socionext,uniphier-system-bus";
85         #address-cells = <2>;
86         #size-cells = <1>;
94             phy-mode = "mii";
101             clock-frequency = <12288000>;