Lines Matching full:pixel

4 $id: http://devicetree.org/schemas/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml#
7 title: Freescale i.MX8qxp Pixel Link Medium Speed Interconnect (MSI) Bus
13   i.MX8qxp pixel link MSI bus is used to control settings of PHYs, I/Os
18   i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. Two input clocks,
29   pixel link MSI bus controller and does not allow SCFW user to control it.
43           - fsl,imx8qxp-display-pixel-link-msi-bus
44           - fsl,imx8qm-display-pixel-link-msi-bus
52           - fsl,imx8qxp-display-pixel-link-msi-bus
53           - fsl,imx8qm-display-pixel-link-msi-bus
94         compatible = "fsl,imx8qxp-display-pixel-link-msi-bus", "simple-pm-bus";
161                 clock-names = "pixel", "bypass";