arm/sunxi/allwinner%2Csun4i-a10-mbus.yaml

4 $id: http://devicetree.org/schemas/arm/sunxi/allwinner,sun4i-a10-mbus.yaml#
7 title: Allwinner Memory Bus (MBUS) controller
14   The MBUS controller drives the MBUS that other devices in the SoC
19   Each device having to perform their DMA through the MBUS must have
20   the interconnects and interconnect-names properties set to the MBUS
27       The content of the cell is the MBUS ID.
31       - allwinner,sun5i-a13-mbus
32       - allwinner,sun8i-a33-mbus
33       - allwinner,sun8i-a50-mbus
34       - allwinner,sun8i-a83t-mbus
35       - allwinner,sun8i-h3-mbus
36       - allwinner,sun8i-r40-mbus
37       - allwinner,sun8i-v3s-mbus
38       - allwinner,sun8i-v536-mbus
39       - allwinner,sun20i-d1-mbus
40       - allwinner,sun50i-a64-mbus
41       - allwinner,sun50i-a100-mbus
42       - allwinner,sun50i-h5-mbus
43       - allwinner,sun50i-h6-mbus
44       - allwinner,sun50i-h616-mbus
45       - allwinner,sun50i-r329-mbus
50       - description: MBUS interconnect/bandwidth limit/PMU registers
56       - const: mbus
62       - description: MBUS interconnect module clock
64       - description: Register bus clock, shared by MBUS and DRAM
69       - const: mbus
76       MBUS PMU activity interrupt.
99             - allwinner,sun5i-a13-mbus
100             - allwinner,sun8i-r40-mbus
142         compatible = "allwinner,sun5i-a13-mbus";
153         compatible = "allwinner,sun50i-a64-mbus";
156         reg-names = "mbus", "dram";
160         clock-names = "mbus", "dram", "bus";