arm/stm32/st%2Cmlahb.yaml

1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 ML-AHB interconnect
10   - Fabien Dessenne <fabien.dessenne@foss.st.com>
11   - Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
14   These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects
15   a Cortex-M subsystem with dedicated memories. The MCU SRAM and RETRAM memory
17   using different buses (see [2]): balancing the Cortex-M firmware accesses
23   - $ref: /schemas/simple-bus.yaml#
29         - st,mlahb
31   dma-ranges:
34       remote Cortex-M processor. Each memory region, is declared with
36       - param 1: device base address (Cortex-M processor address)
37       - param 2: physical base address (local CPU address)
38       - param 3: size of the memory region.
41   '#address-cells':
44   '#size-cells':
48   - compatible
49   - '#address-cells'
50   - '#size-cells'
51   - dma-ranges
56   - |
57     ahb {
58       compatible = "st,mlahb", "simple-bus";
59       #address-cells = <1>;
60       #size-cells = <1>;
62       dma-ranges = <0x00000000 0x38000000 0x10000>,