arm/marvell/cp110-system-controller.txt

4 The CP110 is one of the two core HW blocks of the Marvell Armada 7K/8K
6 giving access to numerous features: clocks, pin-muxing and many other
11  - compatible: must be: "syscon", "simple-mfd";
12  - reg: register area of the CP110 system controller
18 -------
23  - a set of core clocks
24  - a set of gateable clocks
28  - The first cell must be 0 or 1. 0 for the core clocks and 1 for the
30  - The second cell identifies the particular core clock or gateable
34  - Core clocks
35    - 0 0	APLL
36    - 0 1	PPv2 core
37    - 0 2	EIP
38    - 0 3	Core
39    - 0 4	NAND core
40    - 0 5	SDIO core
41  - Gateable clocks
42    - 1 0	Audio
43    - 1 1	Comm Unit
44    - 1 2	NAND
45    - 1 3	PPv2
46    - 1 4	SDIO
47    - 1 5	MG Domain
48    - 1 6	MG Core
49    - 1 7	XOR1
50    - 1 8	XOR0
51    - 1 9	GOP DP
52    - 1 11	PCIe x1 0
53    - 1 12	PCIe x1 1
54    - 1 13	PCIe x4
55    - 1 14	PCIe / XOR
56    - 1 15	SATA
57    - 1 16	SATA USB
58    - 1 17	Main
59    - 1 18	SD/MMC/GOP
60    - 1 21	Slow IO (SPI, NOR, BootROM, I2C, UART)
61    - 1 22	USB3H0
62    - 1 23	USB3H1
63    - 1 24	USB3 Device
64    - 1 25	EIP150
65    - 1 26	EIP197
69  - compatible: must be:
70      "marvell,cp110-clock"
71  - #clock-cells: must be set to 2
74 --------
77 Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt.
81 - compatible: "marvell,armada-7k-pinctrl", "marvell,armada-8k-cpm-pinctrl",
82   "marvell,armada-8k-cps-pinctrl" or "marvell,cp115-standalone-pinctrl"
92 mpp1	1	gpio, dev(ale0), au(i2sdo_spdifo), ge0(rxd2), tdm(drx), ptp(clk), mss_i2c(sck), uart0(txd), …
98 …, dev(ad10), ge0(txd2), spi0(csn1), spi1(csn1), sata0(present_act), led(data), uart0(txd), ptp(clk)
99 …9), ge0(txd1), spi0(csn0), spi1(csn0), uart0(cts), led(stb), uart2(rxd), ptp(pclk_out), synce1(clk)
100 mpp9	9	gpio, dev(ad8), ge0(txd0), spi0(mosi), spi1(mosi), pcie(rstoutn), synce2(clk)
102 mpp11	11	gpio, dev(wen1), ge0(txclkout), spi0(clk), spi1(clk), uart0(rts), led(clk), uart2(txd), sa…
107 mpp16	16	gpio, dev(ad6), spi1(clk), mss_spi(clk)
120 mpp29	29	gpio, dev(csn2), spi1(mosi), mss_gpio6, ge0(rxd1), spi0(csn6), pcie1(clkreq), ptp(clk), ms…
121 …ev(csn3), spi1(clk), mss_gpio7, ge0(rxd0), spi0(csn7), pcie0(clkreq), ptp(pclk_out), mss_i2c(sck),…
126 mpp35	35	gpio, sata1(present_act), i2c1(sda), mss_spi(clk), tdm(pclk), au(i2sdo_spdifo), sdio(card_…
127 mpp36	36	gpio, synce2(clk), i2c1(sck), ptp(clk), synce1(clk), au(i2sbclk), sata0(present_act), xg(m…
130 mpp39	39	gpio, sdio(wr_protect), au(i2sbclk), ptp(clk), spi0(csn1), sata1(present_act), mss_gpio0
131 mpp40	40	gpio, sdio(pwr11), synce1(clk), mss_i2c(sda), au(i2sdo_spdifo), ptp(pclk_out), spi0(clk), …
133 mpp42	42	gpio, sdio(v18_en), sdio(wr_protect), synce2(clk), au(i2smclk), mss_uart(txd), spi0(miso),…
134 mpp43	43	gpio, sdio(card_detect), synce1(clk), au(i2sextclk), mss_uart(rxd), spi0(csn0), uart1(rts)…
138 mpp47	47	gpio, ge1(txd0), spi1(clk), uart1(txd), ge(mdc)
143 mpp52	52	gpio, ge1(rxd1), synce1(clk), synce2(clk), spi1(csn2), uart1(cts), led(clk), pcie(rstoutn)…
144 mpp53	53	gpio, ge1(rxd2), ptp(clk), spi1(csn3), uart1(rxd), led(stb), sdio(led)
145 mpp54	54	gpio, ge1(rxd3), synce2(clk), ptp(pclk_out), synce1(clk), led(data), sdio(hw_rst), sdio_wp…
147 mpp56	56	gpio, tdm(drx), au(i2sdo_spdifo), spi0(clk), uart1(rxd), sata1(present_act), sdio(clk)
149 mpp58	58	gpio, mss_i2c(sck), ptp(clk), tdm(rstn), au(i2sdi), spi0(miso), uart1(cts), led(clk), sdio…
150 mpp59	59	gpio, mss_gpio7, synce2(clk), tdm(fsync), au(i2slrclk), spi0(csn0), uart0(cts), led(stb), …
152 mpp61	61	gpio, mss_gpio5, ptp(clk), tdm(pclk), au(i2sextclk), spi0(csn2), uart0(txd), uart2(txd), s…
153 mpp62	62	gpio, mss_gpio4, synce1(clk), ptp(pclk_out), sata1(present_act), spi0(csn3), uart0(rxd), u…
156 -----
159 Documentation/devicetree/bindings/gpio/gpio-mvebu.yaml.
163 - compatible: "marvell,armada-8k-gpio"
165 - offset: offset address inside the syscon block
169 CP110_LABEL(syscon0): system-controller@440000 {
170 	compatible = "syscon", "simple-mfd";
173 	CP110_LABEL(clk): clock {
174 		compatible = "marvell,cp110-clock";
175 		#clock-cells = <2>;
179 		compatible = "marvell,armada-8k-cpm-pinctrl";
183 		compatible = "marvell,armada-8k-gpio";
186 		gpio-controller;
187 		#gpio-cells = <2>;
188 		gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>;
197 --------
203 critical point to any subnode of the thermal-zone node.
209 - compatible: must be one of:
210   * marvell,armada-cp110-thermal
211 - reg: register range associated with the thermal functions.
214 - interrupts-extended: overheat interrupt handle. Should point to
215   a line of the ICU-SEI irqchip (116 is what is usually used by the
216   firmware). The ICU-SEI will redirect towards interrupt line #37 of the
218   See interrupt-controller/interrupts.txt
219 - #thermal-sensor-cells: shall be <1> when thermal-zones subnodes refer
224 CP110_LABEL(syscon1): system-controller@6f8000 {
225 	compatible = "syscon", "simple-mfd";
228 	CP110_LABEL(thermal): thermal-sensor@70 {
229 		compatible = "marvell,armada-cp110-thermal";
231 		interrupts-extended = <&CP110_LABEL(icu_sei) 116 IRQ_TYPE_LEVEL_HIGH>;
232 		#thermal-sensor-cells = <1>;