arm/calxeda/l2ecc.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Calxeda Highbank L2 cache ECC
10   Binding for the Calxeda Highbank L2 cache controller ECC device.
11   This does not cover the actual L2 cache controller control registers,
15   - Andre Przywara <andre.przywara@arm.com>
19     const: calxeda,hb-sregs-l2-ecc
26       - description: single bit error interrupt
27       - description: double bit error interrupt
30   - compatible
31   - reg
32   - interrupts
37   - |
38     sregs@fff3c200 {
39         compatible = "calxeda,hb-sregs-l2-ecc";