bindings/arm/arm%2Ccoresight-tmc.yaml

1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,coresight-tmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Arm CoreSight Trace Memory Controller
10   - Mathieu Poirier <mathieu.poirier@linaro.org>
11   - Mike Leach <mike.leach@linaro.org>
12   - Leo Yan <leo.yan@linaro.org>
13   - Suzuki K Poulose <suzuki.poulose@arm.com>
16   CoreSight components are compliant with the ARM CoreSight architecture
32         const: arm,coresight-tmc
34     - compatible
37   - $ref: /schemas/arm/primecell.yaml#
42       - const: arm,coresight-tmc
43       - const: arm,primecell
52   clock-names:
55       - const: apb_pclk
56       - const: atclk
61   power-domains:
64   arm,buffer-size:
68       Size of contiguous buffer space for TMC ETR (embedded trace router). The
72   arm,scatter-gather:
75       Indicates that the TMC-ETR can safely use the SG mode on this system.
77   arm,max-burst-size:
79       The maximum burst size initiated by TMC on the AXI master interface. The
85   in-ports:
91         description: Input connection from the CoreSight Trace bus.
94   out-ports:
105   - compatible
106   - reg
107   - clocks
108   - clock-names
109   - in-ports
114   - |
116         compatible = "arm,coresight-tmc", "arm,primecell";
120         clock-names = "apb_pclk";
121         in-ports {
124                     remote-endpoint = <&replicator2_out_port0>;
129         out-ports {
132                     remote-endpoint = <&catu_in_port>;