Lines Matching +full:in +full:- +full:between
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/arm/arm,coresight-cti.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 to one or more CoreSight components and/or a CPU, with CTIs interconnected in
17 The CTI component properties define the connections between the individual
21 number is defined at design time, the maximum of each defined in the DEVID
24 CTIs are interconnected in a star topology via the CTM, using a number of
26 described in the DEVID register. The star topology is not required to be
27 described in the bindings as the actual connections are software
30 In general the connections between CTI and components via the trigger signals
34 In this case the ARM v8 architecture defines the required signal connections
35 between CTI and the CPU core and ETM if present. In the case of a v8
37 indicate this feature (arm,coresight-cti-v8-arch).
44 on the connections between the CTI and other components for correct operation.
45 This information might be found by enabling the Integration Test registers in
46 the driver (set CONFIG_CORESIGHT_CTI_INTEGRATION_TEST in Kernel
48 between CTI and other CoreSight components.
50 Certain triggers between CoreSight devices and the CTI have specific types
52 constants defined in <dt-bindings/arm/coresight-cti-dt.h>
55 is defined in the binding as type PE_EDBGREQ. These types will appear in an
59 Note that some hardware trigger signals can be connected to non-CoreSight
63 - Mike Leach <mike.leach@linaro.org>
66 - $ref: /schemas/arm/primecell.yaml#
74 - arm,coresight-cti
76 - compatible
80 pattern: "^cti(@[0-9a-f]+)$"
83 - items:
84 - const: arm,coresight-cti
85 - const: arm,primecell
86 - items:
87 - const: arm,coresight-cti-v8-arch
88 - const: arm,coresight-cti
89 - const: arm,primecell
98 power-domains:
101 arm,cti-ctm-id:
104 Defines the CTM this CTI is connected to, in large systems with multiple
105 separate CTI/CTM nets. Typically multi-socket systems where the CTM is
106 propagated between sockets.
108 arm,cs-dev-assoc:
113 will be enabled. Use in CTI base node when compatible string
114 arm,coresight-cti-v8-arch used. If the associated device has not been
120 # size cells and address cells required if trig-conns node present.
121 "#size-cells":
124 "#address-cells":
128 '^trig-conns@([0-9]+)$':
134 between this CTI and another hardware device. This device may be a CPU,
147 arm,cs-dev-assoc:
158 arm,trig-in-sigs:
159 $ref: /schemas/types.yaml#/definitions/uint32-array
163 List of CTI trigger in signal numbers in use by a trig-conns node.
165 arm,trig-in-types:
166 $ref: /schemas/types.yaml#/definitions/uint32-array
170 List of constants representing the types for the CTI trigger in
171 signals. Types in this array match to the corresponding signal in the
172 arm,trig-in-sigs array. If the -types array is smaller, or omitted
175 arm,trig-out-sigs:
176 $ref: /schemas/types.yaml#/definitions/uint32-array
180 List of CTI trigger out signal numbers in use by a trig-conns node.
182 arm,trig-out-types:
183 $ref: /schemas/types.yaml#/definitions/uint32-array
188 signals. Types in this array match to the corresponding signal
189 in the arm,trig-out-sigs array. If the "-types" array is smaller,
192 arm,trig-filters:
193 $ref: /schemas/types.yaml#/definitions/uint32-array
200 arm,trig-conn-name:
204 arm,cs-dev-assoc properties are not being used in this connection.
205 Principle use for CTI that are connected to non-CoreSight devices, or
209 - required:
210 - arm,trig-in-sigs
211 - required:
212 - arm,trig-out-sigs
214 - required:
215 - arm,trig-conn-name
216 - required:
217 - cpu
218 - required:
219 - arm,cs-dev-assoc
221 - reg
224 - compatible
225 - reg
226 - clocks
227 - clock-names
233 const: arm,coresight-cti-v8-arch
237 - cpu
243 - |
245 compatible = "arm,coresight-cti", "arm,primecell";
249 clock-names = "apb_pclk";
251 # v8 architecturally defined CTI - CPU + ETM connections generated by the
253 - |
255 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
260 clock-names = "apb_pclk";
263 arm,cs-dev-assoc = <&etm1>;
265 # Implementation defined CTI - CPU + ETM connections explicitly defined..
266 # Shows use of type constants from dt-bindings/arm/coresight-cti-dt.h
267 # #size-cells and #address-cells are required if trig-conns@ nodes present.
268 - |
269 #include <dt-bindings/arm/coresight-cti-dt.h>
272 compatible = "arm,coresight-cti", "arm,primecell";
276 clock-names = "apb_pclk";
278 arm,cti-ctm-id = <1>;
280 #address-cells = <1>;
281 #size-cells = <0>;
283 trig-conns@0 {
285 arm,trig-in-sigs = <4 5 6 7>;
286 arm,trig-in-types = <ETM_EXTOUT
290 arm,trig-out-sigs = <4 5 6 7>;
291 arm,trig-out-types = <ETM_EXTIN
295 arm,cs-dev-assoc = <&etm0>;
298 trig-conns@1 {
301 arm,trig-in-sigs = <0 1>;
302 arm,trig-in-types = <PE_DBGTRIGGER
304 arm,trig-out-sigs = <0 1 2 >;
305 arm,trig-out-types = <PE_EDBGREQ
309 arm,trig-filters = <0>;
312 # Implementation defined CTI - non CoreSight component connections.
313 - |
315 compatible = "arm,coresight-cti", "arm,primecell";
319 clock-names = "apb_pclk";
321 #address-cells = <1>;
322 #size-cells = <0>;
324 trig-conns@0 {
326 arm,trig-in-sigs = <0>;
327 arm,trig-in-types = <GEN_INTREQ>;
328 arm,trig-out-sigs = <0>;
329 arm,trig-out-types = <GEN_HALTREQ>;
330 arm,trig-conn-name = "sys_profiler";
333 trig-conns@1 {
335 arm,trig-out-sigs = <2 3>;
336 arm,trig-out-types = <GEN_HALTREQ GEN_RESTARTREQ>;
337 arm,trig-conn-name = "watchdog";
340 trig-conns@2 {
342 arm,trig-in-sigs = <1 6>;
343 arm,trig-in-types = <GEN_HALTREQ GEN_RESTARTREQ>;
344 arm,trig-conn-name = "g_counter";