Lines Matching +full:max +full:- +full:memory +full:- +full:bandwidth
1 .. SPDX-License-Identifier: GPL-2.0
9 :Authors: - Fenghua Yu <fenghua.yu@intel.com>
10 - Tony Luck <tony.luck@intel.com>
11 - Vikas Shivappa <vikas.shivappa@intel.com>
25 MBM (Memory Bandwidth Monitoring) "cqm_mbm_total", "cqm_mbm_local"
26 MBA (Memory Bandwidth Allocation) "mba"
27 SMBA (Slow Memory Bandwidth Allocation) ""
28 BMEC (Bandwidth Monitoring Event Configuration) ""
38 # mount -t resctrl resctrl [-o cdp[,cdpl2][,mba_MBps][,debug]] /sys/fs/resctrl
48 bandwidth in MiBps
57 pseudo-locking is a unique way of using cache control to "pin" or
59 "Cache Pseudo-Locking".
96 own settings for cache use which can over-ride
128 Corresponding region is pseudo-locked. No
131 Indicates if non-contiguous 1s value in CBM is supported.
136 Non-contiguous 1s value in CBM is supported.
138 Memory bandwidth(MB) subdirectory contains the following files
142 The minimum memory bandwidth percentage which
146 The granularity in which the memory bandwidth
150 available bandwidth control steps are:
155 non-linear. This field is purely informational
161 request different memory bandwidth percentages:
163 "max":
166 "per-thread":
167 bandwidth percentages are directly applied to
188 If the system supports Bandwidth Monitoring Event
189 Configuration (BMEC), then the bandwidth events will
201 and mbm_local_bytes events, respectively, when the Bandwidth
205 changed, the bandwidth counters for all RMIDs of both events
215 6 Dirty Victims from the QOS domain to all types of memory
216 5 Reads to slow memory in the non-local NUMA domain
217 4 Reads to slow memory in the local NUMA domain
218 3 Non-temporal writes to non-local NUMA domain
219 2 Non-temporal writes to local NUMA domain
220 1 Reads to memory in the non-local NUMA domain
221 0 Reads to memory in the local NUMA domain
226 0x15 to count all the local memory events.
249 * To change the mbm_local_bytes to count all the slow memory reads on
262 counter can be considered for re-use.
275 mask f7 has non-consecutive 1-bits
332 When the resource group is in pseudo-locked mode this file will
334 pseudo-locked region.
345 Each resource has its own line and format - see below for details.
356 cache pseudo-locked region is created by first writing
357 "pseudo-locksetup" to the "mode" file before writing the cache
358 pseudo-locked region's schemata to the resource group's "schemata"
359 file. On successful pseudo-locked region creation the mode will
360 automatically change to "pseudo-locked".
378 On systems with Sub-NUMA Cluster (SNC) enabled there are extra
388 -------------------------
393 1) If the task is a member of a non-default group, then the schemata
403 -------------------------
404 1) If a task is a member of a MON group, or non-default CTRL_MON group
425 are evicted and re-used while the occupancy in the new group rises as
426 the task accesses memory and loads into the cache are counted based on
440 max_threshold_occupancy - generic concepts
441 ------------------------------------------
447 limbo RMIDs but which are not ready to be used, user may see an -EBUSY
459 Schemata files - general concepts
460 ---------------------------------
466 ---------
478 ---------------------
485 0x3, 0x6 and 0xC are legal 4-bit masks with two bits set, but 0x5, 0x9
487 if non-contiguous 1s value is supported. On a system with a 20-bit mask
491 Notes on Sub-NUMA Cluster mode
493 When SNC mode is enabled, Linux may load balance tasks between Sub-NUMA
495 on Sub-NUMA nodes share the same L3 cache and the system may report
496 the NUMA distance between Sub-NUMA nodes with a lower value than used
499 The top-level monitoring files in each "mon_L3_XX" directory provide
501 Users who bind tasks to the CPUs of a specific Sub-NUMA node can read
505 Memory bandwidth allocation is still performed at the L3 cache
510 of SNC nodes per L3 cache. E.g. with a 100MB cache on a system with 10-bit
514 Memory bandwidth Allocation and monitoring
517 For Memory bandwidth resource, by default the user controls the resource
518 by indicating the percentage of total memory bandwidth.
520 The minimum bandwidth percentage value for each cpu model is predefined
521 and can be looked up through "info/MB/min_bandwidth". The bandwidth
523 be looked up at "info/MB/bandwidth_gran". The available bandwidth
527 The bandwidth throttling is a core specific mechanism on some of Intel
528 SKUs. Using a high bandwidth and a low bandwidth setting on two threads
530 low bandwidth (see "thread_throttle_mode").
532 The fact that Memory bandwidth allocation(MBA) may be a core
533 specific mechanism where as memory bandwidth monitoring(MBM) is done at
535 via the MBA and then monitor the bandwidth to see if the controls are
538 1. User may *not* see increase in actual bandwidth when percentage
541 This can occur when aggregate L2 external bandwidth is more than L3
542 external bandwidth. Consider an SKL SKU with 24 cores on a package and
543 where L2 external is 10GBps (hence aggregate L2 external bandwidth is
544 240GBps) and L3 external bandwidth is 100GBps. Now a workload with '20
545 threads, having 50% bandwidth, each consuming 5GBps' consumes the max L3
546 bandwidth of 100GBps although the percentage value specified is only 50%
547 << 100%. Hence increasing the bandwidth percentage will not yield any
548 more bandwidth. This is because although the L2 external bandwidth still
549 has capacity, the L3 external bandwidth is fully used. Also note that
552 2. Same bandwidth percentage may mean different actual bandwidth
555 For the same SKU in #1, a 'single thread, with 10% bandwidth' and '4
556 thread, with 10% bandwidth' can consume upto 10GBps and 40GBps although
557 they have same percentage bandwidth of 10%. This is simply because as
558 threads start using more cores in an rdtgroup, the actual bandwidth may
559 increase or vary although user specified bandwidth percentage is same.
562 resctrl added support for specifying the bandwidth in MiBps as well. The
564 Controller(mba_sc)" which reads the actual bandwidth using MBM counters
565 and adjust the memory bandwidth percentages to ensure::
567 "actual bandwidth < user specified bandwidth".
569 By default, the schemata would take the bandwidth percentage values
575 ----------------------------------------------------------------
581 ------------------------------------------------------------------
589 ------------------------
601 Memory bandwidth Allocation (default mode)
602 ------------------------------------------
604 Memory b/w domain is L3 cache.
609 Memory bandwidth Allocation specified in MiBps
610 ----------------------------------------------
612 Memory bandwidth domain is L3 cache.
617 Slow Memory Bandwidth Allocation (SMBA)
618 ---------------------------------------
619 AMD hardware supports Slow Memory Bandwidth Allocation (SMBA).
620 CXL.memory is the only supported "slow" memory device. With the
621 support of SMBA, the hardware enables bandwidth allocation on
622 the slow memory devices. If there are multiple such devices in
626 The presence of SMBA (with CXL.memory) is independent of slow memory
630 The bandwidth domain for slow memory is L3 cache. Its schemata file
637 ---------------------------------
652 --------------------------------------------------
653 Reading the schemata file will show the current bandwidth limit on all
656 configure the bandwidth limit.
672 --------------------------------------------------------------------
691 Cache Pseudo-Locking
694 application can fill. Cache pseudo-locking builds on the fact that a
695 CPU can still read and write data pre-allocated outside its current
696 allocated area on a cache hit. With cache pseudo-locking, data can be
699 pseudo-locked memory is made accessible to user space where an
701 a region of memory with reduced average read latency.
703 The creation of a cache pseudo-locked region is triggered by a request
705 to be pseudo-locked. The cache pseudo-locked region is created as follows:
707 - Create a CAT allocation CLOSNEW with a CBM matching the schemata
708 from the user of the cache region that will contain the pseudo-locked
709 memory. This region must not overlap with any current CAT allocation/CLOS
711 while the pseudo-locked region exists.
712 - Create a contiguous region of memory of the same size as the cache
714 - Flush the cache, disable hardware prefetchers, disable preemption.
715 - Make CLOSNEW the active CLOS and touch the allocated memory to load
717 - Set the previous CLOS as active.
718 - At this point the closid CLOSNEW can be released - the cache
719 pseudo-locked region is protected as long as its CBM does not appear in
720 any CAT allocation. Even though the cache pseudo-locked region will from
722 any CLOS will be able to access the memory in the pseudo-locked region since
724 - The contiguous region of memory loaded into the cache is exposed to
725 user-space as a character device.
727 Cache pseudo-locking increases the probability that data will remain
731 “locked” data from cache. Power management C-states may shrink or
732 power off cache. Deeper C-states will automatically be restricted on
733 pseudo-locked region creation.
735 It is required that an application using a pseudo-locked region runs
737 with the cache on which the pseudo-locked region resides. A sanity check
738 within the code will not allow an application to map pseudo-locked memory
740 pseudo-locked region resides. The sanity check is only done during the
744 Pseudo-locking is accomplished in two stages:
747 of cache that should be dedicated to pseudo-locking. At this time an
748 equivalent portion of memory is allocated, loaded into allocated
750 2) During the second stage a user-space application maps (mmap()) the
751 pseudo-locked memory into its address space.
753 Cache Pseudo-Locking Interface
754 ------------------------------
755 A pseudo-locked region is created using the resctrl interface as follows:
758 2) Change the new resource group's mode to "pseudo-locksetup" by writing
759 "pseudo-locksetup" to the "mode" file.
760 3) Write the schemata of the pseudo-locked region to the "schemata" file. All
764 On successful pseudo-locked region creation the "mode" file will contain
765 "pseudo-locked" and a new character device with the same name as the resource
767 by user space in order to obtain access to the pseudo-locked memory region.
769 An example of cache pseudo-locked region creation and usage can be found below.
771 Cache Pseudo-Locking Debugging Interface
772 ----------------------------------------
773 The pseudo-locking debugging interface is enabled by default (if
776 There is no explicit way for the kernel to test if a provided memory
777 location is present in the cache. The pseudo-locking debugging interface uses
779 the pseudo-locked region:
781 1) Memory access latency using the pseudo_lock_mem_latency tracepoint. Data
783 example below). In this test the pseudo-locked region is traversed at
791 When a pseudo-locked region is created a new debugfs directory is created for
793 write-only file, pseudo_lock_measure, is present in this directory. The
794 measurement of the pseudo-locked region depends on the number written to this
815 In this example a pseudo-locked region named "newlock" was created. Here is
849 In this example a pseudo-locked region named "newlock" was created on the L2
862 # _-----=> irqs-off
863 # / _----=> need-resched
864 # | / _---=> hardirq/softirq
865 # || / _--=> preempt-depth
867 # TASK-PID CPU# |||| TIMESTAMP FUNCTION
869 pseudo_lock_mea-1672 [002] .... 3132.860500: pseudo_lock_l2: hits=4097 miss=0
878 for cache bit masks, minimum b/w of 10% with a memory bandwidth
882 # mount -t resctrl resctrl /sys/fs/resctrl
896 maximum memory b/w of 50% on socket0 and 50% on socket 1.
897 Tasks in group "p1" may also use 50% memory b/w on both sockets.
898 Note that unlike cache masks, memory b/w cannot specify whether these
904 max b/w in MB rather than the percentage values.
910 In the above example the tasks in "p1" and "p0" on socket 0 would use a max b/w
915 Again two sockets, but this time with a more realistic 20-bit mask.
918 processor 1 on socket 0 on a 2-socket and dual core machine. To avoid noisy
919 neighbors, each of the two real-time tasks exclusively occupies one quarter
923 # mount -t resctrl resctrl /sys/fs/resctrl
927 50% of the L3 cache on socket 0 and 50% of memory b/w cannot be used by
946 # taskset -cp 1 1234
953 # taskset -cp 2 5678
955 For the same 2 socket system with memory b/w resource and CAT L3 the
959 For our first real time task this would request 20% memory b/w on socket 0.
962 # echo -e "L3:0=f8000;1=fffff\nMB:0=20;1=100" > p0/schemata
964 For our second real time task this would request an other 20% memory b/w
968 # echo -e "L3:0=f8000;1=fffff\nMB:0=20;1=100" > p0/schemata
972 A single socket system which has real-time tasks running on core 4-7 and
973 non real-time workload assigned to core 0-3. The real-time tasks share text
979 # mount -t resctrl resctrl /sys/fs/resctrl
983 50% of the L3 cache on socket 0, and 50% of memory bandwidth on socket 0
989 to the "top" 50% of the cache on socket 0 and 50% of memory bandwidth on
996 Finally we move core 4-7 over to the new group and make sure that the
998 also get 50% of memory bandwidth assuming that the cores 4-7 are SMT
999 siblings and only the real time threads are scheduled on the cores 4-7.
1012 system with two L2 cache instances that can be configured with an 8-bit
1017 # mount -t resctrl resctrl /sys/fs/resctrl/
1034 -sh: echo: write error: Invalid argument
1069 -sh: echo: write error: Invalid argument
1073 Example of Cache Pseudo-Locking
1075 Lock portion of L2 cache from cache id 1 using CBM 0x3. Pseudo-locked
1080 # mount -t resctrl resctrl /sys/fs/resctrl/
1083 Ensure that there are bits available that can be pseudo-locked, since only
1084 unused bits can be pseudo-locked the bits to be pseudo-locked needs to be
1093 Create a new resource group that will be associated with the pseudo-locked
1094 region, indicate that it will be used for a pseudo-locked region, and
1095 configure the requested pseudo-locked region capacity bitmask::
1098 # echo pseudo-locksetup > newlock/mode
1101 On success the resource group's mode will change to pseudo-locked, the
1102 bit_usage will reflect the pseudo-locked region, and the character device
1103 exposing the pseudo-locked region will exist::
1106 pseudo-locked
1109 # ls -l /dev/pseudo_lock/newlock
1110 crw------- 1 root root 243, 0 Apr 3 05:01 /dev/pseudo_lock/newlock
1115 * Example code to access one page of pseudo-locked cache region
1128 * cores associated with the pseudo-locked region. Here the cpu
1165 /* Application interacts with pseudo-locked memory @mapping */
1179 ----------------------------
1187 1. Read the cbmmasks from each directory or the per-resource "bit_usage"
1218 $ flock -s /sys/fs/resctrl/ find /sys/fs/resctrl
1222 $ cat create-dir.sh
1224 mask = function-of(output.txt)
1228 $ flock /sys/fs/resctrl/ ./create-dir.sh
1247 exit(-1);
1259 exit(-1);
1271 exit(-1);
1280 if (fd == -1) {
1282 exit(-1);
1296 ----------------------
1303 ------------------------------------------------------------------------
1307 # mount -t resctrl resctrl /sys/fs/resctrl
1347 --------------------------------------------
1350 # mount -t resctrl resctrl /sys/fs/resctrl
1367 ---------------------------------------------------------------------
1378 # mount -t resctrl resctrl /sys/fs/resctrl
1402 -----------------------------------
1404 A single socket system which has real time tasks running on cores 4-7
1409 # mount -t resctrl resctrl /sys/fs/resctrl
1413 Move the cpus 4-7 over to p1::
1425 Intel MBM Counters May Report System Memory Bandwidth Incorrectly
1426 -----------------------------------------------------------------
1430 Problem: Intel Memory Bandwidth Monitoring (MBM) counters track metrics
1433 metrics, may report incorrect system bandwidth for certain RMID values.
1435 Implication: Due to the errata, system memory bandwidth may not match
1441 +---------------+---------------+---------------+-----------------+
1443 +---------------+---------------+---------------+-----------------+
1445 +---------------+---------------+---------------+-----------------+
1447 +---------------+---------------+---------------+-----------------+
1449 +---------------+---------------+---------------+-----------------+
1451 +---------------+---------------+---------------+-----------------+
1453 +---------------+---------------+---------------+-----------------+
1455 +---------------+---------------+---------------+-----------------+
1457 +---------------+---------------+---------------+-----------------+
1459 +---------------+---------------+---------------+-----------------+
1461 +---------------+---------------+---------------+-----------------+
1463 +---------------+---------------+---------------+-----------------+
1465 +---------------+---------------+---------------+-----------------+
1467 +---------------+---------------+---------------+-----------------+
1469 +---------------+---------------+---------------+-----------------+
1471 +---------------+---------------+---------------+-----------------+
1473 +---------------+---------------+---------------+-----------------+
1475 +---------------+---------------+---------------+-----------------+
1477 +---------------+---------------+---------------+-----------------+
1479 +---------------+---------------+---------------+-----------------+
1481 +---------------+---------------+---------------+-----------------+
1483 +---------------+---------------+---------------+-----------------+
1485 +---------------+---------------+---------------+-----------------+
1487 +---------------+---------------+---------------+-----------------+
1489 +---------------+---------------+---------------+-----------------+
1491 +---------------+---------------+---------------+-----------------+
1493 +---------------+---------------+---------------+-----------------+
1495 +---------------+---------------+---------------+-----------------+
1497 +---------------+---------------+---------------+-----------------+
1505 …958/https://www.intel.com/content/www/us/en/processors/xeon/scalable/xeon-scalable-spec-update.html
1507 2. Erratum BDF102 in Intel Xeon E5-2600 v4 Processor Product Family Specification Update:
1508 …w.intel.com/content/dam/www/public/us/en/documents/specification-updates/xeon-e5-v4-spec-update.pdf
1511 …are.intel.com/content/www/us/en/develop/articles/intel-resource-director-technology-rdt-reference-…