arch/x86/buslock.rst

1 .. SPDX-License-Identifier: GPL-2.0
6 Bus lock detection and handling
10 :Authors: - Fenghua Yu <fenghua.yu@intel.com>
11           - Tony Luck <tony.luck@intel.com>
18 the system locks the bus while the CPU accesses the two cache lines.
20 A bus lock is acquired through either split locked access to writeback (WB)
21 memory or any locked access to non-WB memory. This is typically thousands of
23 performance on other cores and brings the whole system to its knees.
29 mechanisms to detect split locks and bus locks.
32 --------------------------------------
37 #DB exception for bus lock detection
38 ------------------------------------
41 instruction acquires a bus lock and is executed. This allows the kernel to
47 The kernel #AC and #DB handlers handle bus lock based on the kernel
50 +------------------+----------------------------+-----------------------+
51 |split_lock_detect=|#AC for split lock		|#DB for bus lock	|
52 +------------------+----------------------------+-----------------------+
54 +------------------+----------------------------+-----------------------+
66 +------------------+----------------------------+-----------------------+
71 +------------------+----------------------------+-----------------------+
72 |ratelimit:N	   |Do nothing			|Limit bus lock rate to	|
73 |(0 < N <= 1000)   |				|N bus locks per second	|
74 |		   |				|system wide and warn on|
75 |		   |				|bus locks.		|
76 +------------------+----------------------------+-----------------------+
81 Detecting and handling bus lock may find usages in various areas:
83 It is critical for real time system designers who build consolidated real
86 to have any bus lock from the untrusted processes to hurt real time
89 generating split lock and bus lock to block the hard real time code to
90 access memory during bus locking.
93 applications from slowing down the overall system by executing instructions
94 with bus lock.
100 ---
102 Disable checking for split lock and bus lock. This option can be useful if
107 ----
109 A warning is emitted when a bus lock is detected which allows to identify
113 -----
115 In this case, the bus lock is not tolerated and the process is killed.
118 ---------
120 A system wide bus lock rate limit N is specified where 0 < N <= 1000. This
121 allows a bus lock rate up to N bus locks per second. When the bus lock rate
130 Selecting a rate limit of 1000 allows the bus to be locked for up to about
131 seven million cycles each second (assuming 7000 cycles for each bus
132 lock). On a 2 GHz processor that would be about 0.35% system slowdown.