Lines Matching +full:non +full:- +full:configurable

57     - For DMA we then provide an entire address space for each PE that can
60 translation table), which has various configurable characteristics
63 - For MSIs, we have two windows in the address space (one at the top of
64 the 32-bit space and one much higher) which, via a combination of the
70 - Error messages just use the RTT.
77 First what they have in common: they forward a configurable portion of
81 - The M32 window:
86 them with a configurable value. This is typically used to generate
87 32-bit PCIe accesses. We configure that window at boot from FW and
101 SR-IOV). We basically use the trick of forcing the bridge MMIO windows
110 - The M64 windows:
127 for large BARs in 64-bit space:
139 - We do the PE# allocation *after* the 64-bit space has been assigned
141 update the M32 PE# for the devices that use both 32-bit and 64-bit
142 spaces or assign the remaining PE# to 32-bit only devices.
144 - We cannot "group" segments in HW, so if a device ends up using more
160 3. Considerations for SR-IOV on PowerKVM
163 * SR-IOV Background
165 The PCIe SR-IOV feature allows a single Physical Function (PF) to
166 support several Virtual Functions (VFs). Registers in the PF's SR-IOV
171 a non-VF device, software uses BARs in the config space header to
173 software uses VF BAR registers in the *PF* SR-IOV Capability to
175 header are read-only zeros.
177 When a VF BAR in the PF SR-IOV Capability is programmed, it sets the
179 PF SR-IOV Capability is programmed to enable eight VFs, and it has a
188 - M32 window: There's one M32 window, and it is split into 256
189 equally-sized segments. The finest granularity possible is a 256MB
198 - Non-segmented M64 window: A non-segmented M64 window is mapped entirely
201 - Single segmented M64 windows: A segmented M64 window could be used just
207 - Multiple segmented M64 windows: As usual, each window is split into 256
208 equally-sized segments, and the segment number is the PE#. But if we
214 Finally, the plan to use M64 windows for SR-IOV, which will be described
227 SR-IOV VF BARs are all the same size.
239 0 1 total_VFs - 1
240 +------+------+- -+------+------+
242 +------+------+- -+------+------+
246 0 1 total_VFs - 1 255
247 +------+------+- -+------+------+- -+------+------+
249 +------+------+- -+------+------+- -+------+------+
258 0 1 total_VFs - 1 255
259 +------+------+- -+------+------+- -+------+------+
261 +------+------+- -+------+------+- -+------+------+
265 0 1 total_VFs - 1 255
266 +------+------+- -+------+------+- -+------+------+
268 +------+------+- -+------+------+- -+------+------+
275 assigned to this one SR-IOV device and none of the space will be
278 respond to segments [0, total_VFs - 1]. There's nothing in hardware that
284 The PCIe SR-IOV spec requires that the base of the VF(n) BAR space be
305 allocate 256 segments, there are (256 - numVFs) choices for the PE# of VF0.