Lines Matching full:but

29 state bits (one for MMIO and one for DMA, they get set together but can be
34 captures things like the details of the error that caused the freeze etc., but
53     memory but accessed in HW by the chip) that provides a direct
91 	reserved for MSIs but this is not a problem at this point; we just
106     but that would mean using a completely different address allocation
116 	bits which are not conveyed by PowerBus but we don't use this.
146       mechanism to make the freeze state cascade to "companion" PEs but
149       SW.  We lose a bit of effectiveness of EEH in that case, but that's
158     sense, but we haven't done it yet.
170     PCI devices, but the BARs in VF config space headers are unusual.  For
193     flexible, but it works best when all the VF BARs are the same size.  If
202     like the M32 window, but the segments can't be individually mapped to
208     equally-sized segments, and the segment number is the PE#.  But if we
229   But doing so introduces another problem: total_VFs is usually smaller
290 set the PE# for the window.  But if it's in a segmented M64 window, the
309 possible, but the isolation isn't as good, and it reduces the number of PE#