Lines Matching full:processor
80 The processor is PowerPC 601.
93 The processor is 40x or 44x family.
97 The processor has a unified L1 cache for instructions and data, as
99 Unused in the kernel since 39c8bf2b3cc1 ("powerpc: Retire e200 core (mpc555x processor)")
112 This is a 601 specific HWCAP, so if it is known that the processor
118 The processor is POWER4 or PPC970/FX/MP.
122 The processor is POWER5.
125 The processor is POWER5+.
128 The processor is Cell.
131 The processor implements the embedded category ("BookE") architecture.
134 The processor implements SMT.
137 The processor icache is coherent with the dcache, and instruction storage
139 instructions with the sequence (as described in, e.g., POWER9 Processor
147 The processor supports the v2.05 userlevel architecture. Processors
151 The processor is PA6T.
157 The processor is POWER6.
160 The processor supports the v2.06 userlevel architecture. Processors
167 The processor supports architected PMU events in the range 0xE0-0xFF.
170 The processor supports true little-endian mode.
173 The processor supports "PowerPC Little-Endian", that uses address
182 The processor supports the v2.07 userlevel architecture. Processors
209 The processor supports the v3.0B / v3.0C userlevel architecture. Processors
228 The processor supports the v3.1 userlevel architecture. Processors