arch/loongarch/irq-chip-model.rst

1 .. SPDX-License-Identifier: GPL-2.0
7 Currently, LoongArch based processors (e.g. Loongson-3A5000) can only work together
10 I/O Interrupt Controller), HTVECINTC (Hyper-Transport Vector Interrupt Controller),
11 PCH-PIC (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
12 in LS7A chipset) and PCH-MSI (MSI Interrupt Controller).
14 CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are per-package
15 controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are controllers out of CPU (i.e.,
22 In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
24 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go
27      +-----+     +---------+     +-------+
28      | IPI | --> | CPUINTC | <-- | Timer |
29      +-----+     +---------+     +-------+
32                  +---------+     +-------+
33                  | LIOINTC | <-- | UARTs |
34                  +---------+     +-------+
37                 +-----------+
39                 +-----------+
42            +---------+ +---------+
43            | PCH-PIC | | PCH-MSI |
44            +---------+ +---------+
47      +---------+ +---------+ +---------+
48      | PCH-LPC | | Devices | | Devices |
49      +---------+ +---------+ +---------+
52      +---------+
54      +---------+
59 In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
61 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by EIOINTC, and then go to
64           +-----+     +---------+     +-------+
65           | IPI | --> | CPUINTC | <-- | Timer |
66           +-----+     +---------+     +-------+
69                 +---------+ +---------+     +-------+
70                 | EIOINTC | | LIOINTC | <-- | UARTs |
71                 +---------+ +---------+     +-------+
74           +---------+ +---------+
75           | PCH-PIC | | PCH-MSI |
76           +---------+ +---------+
79     +---------+ +---------+ +---------+
80     | PCH-LPC | | Devices | | Devices |
81     +---------+ +---------+ +---------+
84     +---------+
86     +---------+
91 In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
92 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, PCH-MSI interrupts go
94 go to PCH-PIC/PCH-LPC and gathered by EIOINTC, and then go to CPUINTC directly::
96  +-----+     +-----------------------+     +-------+
97  | IPI | --> |        CPUINTC        | <-- | Timer |
98  +-----+     +-----------------------+     +-------+
101        +---------+ +----------+ +---------+     +-------+
102        | EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs |
103        +---------+ +----------+ +---------+     +-------+
106        +---------+  +---------+
107        | PCH-PIC |  | PCH-MSI |
108        +---------+  +---------+
111  +---------+ +---------+ +---------+
112  | Devices | | PCH-LPC | | Devices |
113  +---------+ +---------+ +---------+
116              +---------+
118              +---------+
120 ACPI-related definitions
147 PCH-PIC::
153 PCH-MSI::
159 PCH-LPC::
168 Documentation of Loongson-3A5000:
170 …https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-userm…
172 …https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-userm…
176 …https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-userm…
178 …https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-userm…
181     - CPUINTC is CSR.ECFG/CSR.ESTAT and its interrupt controller described
182       in Section 7.4 of "LoongArch Reference Manual, Vol 1";
183     - LIOINTC is "Legacy I/OInterrupts" described in Section 11.1 of
185     - EIOINTC is "Extended I/O Interrupts" described in Section 11.2 of
187     - HTVECINTC is "HyperTransport Interrupts" described in Section 14.3 of
189     - PCH-PIC/PCH-MSI is "Interrupt Controller" described in Section 5 of
191     - PCH-LPC is "LPC Interrupts" described in Section 24.3 of