arch/loongarch/irq-chip-model.rst

9 Interrupt Controller), LIOINTC (Legacy I/O Interrupt Controller), EIOINTC (Extended
14 CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are per-package
23 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
25 to LIOINTC, and then CPUINTC::
33                  | LIOINTC | <-- | UARTs |
60 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
70                 | EIOINTC | | LIOINTC | <-- | UARTs |
92 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, PCH-MSI interrupts go
102        | EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs |
129 LIOINTC::
183     - LIOINTC is "Legacy I/OInterrupts" described in Section 11.1 of