Lines Matching +full:loongson +full:- +full:1 +full:b
1 .. SPDX-License-Identifier: GPL-2.0
7 LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V. There are
8 currently 3 variants: a reduced 32-bit version (LA32R), a standard 32-bit
9 version (LA32S) and a 64-bit version (LA64). There are 4 privilege levels
22 ----
24 LoongArch has 32 GPRs ( ``$r0`` ~ ``$r31`` ); each one is 32-bit wide in LA32
25 and 64-bit wide in LA64. ``$r0`` is hard-wired to zero, and the other registers
26 are not architecturally special. (Except ``$r1``, which is hard-wired as the
30 the LoongArch ELF psABI spec, in :ref:`References <loongarch-references>`:
40 ``$r4``-``$r11`` ``$a0``-``$a7`` Argument registers No
41 ``$r4``-``$r5`` ``$v0``-``$v1`` Return value No
42 ``$r12``-``$r20`` ``$t0``-``$t8`` Temp registers No
45 ``$r23``-``$r31`` ``$s0``-``$s8`` Static registers Yes
56 ----
59 64-bit wide on the LA64 cores.
61 The floating-point register convention is the same as described in the
68 ``$f0``-``$f7`` ``$fa0``-``$fa7`` Argument registers No
69 ``$f0``-``$f1`` ``$fv0``-``$fv1`` Return value No
70 ``$f8``-``$f23`` ``$ft0``-``$ft15`` Temp registers No
71 ``$f24``-``$f31`` ``$fs0``-``$fs7`` Static registers Yes
79 ----
83 - LSX (Loongson SIMD eXtension) with 128-bit vectors,
84 - LASX (Loongson Advanced SIMD eXtension) with 256-bit vectors.
94 ----
102 0x1 Pre-exception Mode Information PRMD
112 0x11 TLB Entry High-order Bits TLBEHI
113 0x12 TLB Entry Low-order Bits 0 TLBELO0
114 0x13 TLB Entry Low-order Bits 1 TLBELO1
117 Lower-half Address Space
119 Higher-half Address Space
121 0x1C Page Walk Control for Lower- PWCL
123 0x1D Page Walk Control for Higher- PWCH
128 0x21 Privileged Resource Configuration 1 PRCFG1
138 0x80 Implementation-specific Control 1 IMPCTL1
139 0x81 Implementation-specific Control 2 IMPCTL2
147 0x8C TLB Refill Exception Entry Low-order TLBRELO0
149 0x8D TLB Refill Exception Entry Low-order TLBRELO1
150 Bits 1
151 0x8E TLB Refill Exception Entry High-order TLBEHI
153 0x8F TLB Refill Exception Pre-exception TLBRPRMD
156 0x91 Machine Error Information 1 MERRINFO1
173 Configuration 1
185 Configuration 1
204 -------------------
219 1RI21 Opcode + I21L + Rj + I21H
230 --------------------
233 :ref:`References <loongarch-references>` for details.
236 1. Arithmetic Instructions::
246 2. Bit-shift Instructions::
251 3. Bit-manipulation Instructions::
253 EXT.W.B EXT.W.H CLO.W CLO.D SLZ.W CLZ.D CTO.W CTO.D CTZ.W CTZ.D
255 REVB.2H REVB.4H REVB.2W REVB.D REVH.2W REVH.D BITREV.4B BITREV.8B BITREV.W BITREV.D
260 BEQ BNE BLT BGE BLTU BGEU BEQZ BNEZ B BL JIRL
264 LD.B LD.BU LD.H LD.HU LD.W LD.WU LD.D ST.B ST.H ST.W ST.D
265 LDX.B LDX.BU LDX.H LDX.HU LDX.W LDX.WU LDX.D STX.B STX.H STX.W STX.D
287 IOCSRRD.B IOCSRRD.H IOCSRRD.W IOCSRRD.D IOCSRWR.B IOCSRWR.H IOCSRWR.W IOCSRWR.D
293 LoongArch supports direct-mapped virtual memory and page-mapped virtual memory.
295 Direct-mapped virtual memory is configured by CSR.DMWn (n=0~3), it has a simple
300 Page-mapped virtual memory has arbitrary relationship between VA and PA, which
301 is recorded in TLB and page tables. LoongArch's TLB includes a fully-associative
302 MTLB (Multiple Page Size TLB) and set-associative STLB (Single Page Size TLB).
309 ``UVRANGE`` ``0x00000000 - 0x7FFFFFFF`` Page-mapped, Cached, PLV0~3
310 ``KPRANGE0`` ``0x80000000 - 0x9FFFFFFF`` Direct-mapped, Uncached, PLV0
311 ``KPRANGE1`` ``0xA0000000 - 0xBFFFFFFF`` Direct-mapped, Cached, PLV0
312 ``KVRANGE`` ``0xC0000000 - 0xFFFFFFFF`` Page-mapped, Cached, PLV0
315 User mode (PLV3) can only access UVRANGE. For direct-mapped KPRANGE0 and
317 direct-mapped VA of 0x00001000 is 0x80001000, and the cached direct-mapped
325 ``XUVRANGE`` ``0x0000000000000000 - Page-mapped, Cached, PLV0~3
327 ``XSPRANGE`` ``0x4000000000000000 - Direct-mapped, Cached / Uncached, PLV0
329 ``XKPRANGE`` ``0x8000000000000000 - Direct-mapped, Cached / Uncached, PLV0
331 ``XKVRANGE`` ``0xC000000000000000 - Page-mapped, Cached, PLV0
335 User mode (PLV3) can only access XUVRANGE. For direct-mapped XSPRANGE and
337 is configured by bits 60~61 in VA: 0 is for strongly-ordered uncached, 1 is
338 for coherent cached, and 2 is for weakly-ordered uncached.
342 To put this in action: the strongly-ordered uncached direct-mapped VA (in
344 direct-mapped VA (in XKPRANGE) of 0x00000000_00001000 is 0x90000000_00001000,
345 and the weakly-ordered uncached direct-mapped VA (in XKPRANGE) of 0x00000000
348 Relationship of Loongson and LoongArch
352 Loongson is a family of processors. Loongson includes 3 series: Loongson-1 is
353 the 32-bit processor series, Loongson-2 is the low-end 64-bit processor series,
354 and Loongson-3 is the high-end 64-bit processor series. Old Loongson is based on
355 MIPS, while New Loongson is based on LoongArch. Take Loongson-3 as an example:
356 Loongson-3A1000/3B1500/3A2000/3A3000/3A4000 are MIPS-compatible, while Loongson-
359 .. _loongarch-references:
364 Official web site of Loongson Technology Corp. Ltd.:
366 http://www.loongson.cn/
368 Developer web site of Loongson and LoongArch (Software and Documentation):
372 https://github.com/loongson/
374 https://loongson.github.io/LoongArch-Documentation/
378 …https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-Vol1-v1.10-…
380 …https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-Vol1-v1.10-…
384 …https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-ELF-ABI-v2.…
386 …https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-ELF-ABI-v2.…
388 Linux kernel repository of Loongson and LoongArch:
390 https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson.git