arch/arm64/sve.rst

2 Scalable Vector Extension support for AArch64 Linux
10 order to support use of the ARM Scalable Vector Extension (SVE), including
25 * SVE registers Z0..Z31, P0..P15 and FFR and the current vector length VL, are
32 * The presence of SVE is reported to userspace via HWCAP_SVE in the aux vector
46   be reported in the AT_HWCAP2 aux vector entry.  In addition to this,
64   reported in the AT_HWCAP2 aux vector entry.  Among other things SME adds
66   separate SME vector length and the same Z/V registers.  See sme.rst
90 2.  Vector length terminology
93 The size of an SVE vector (Z) register is referred to as the "vector length".
95 To avoid confusion about the units used to express vector length, the kernel
98 * Vector length (VL) = size of a Z-register in bytes
100 * Vector quadwords (VQ) = size of a Z-register in units of 128 bits
120 * All other SVE state of a thread, including the currently configured vector
121   length, the state of the PR_SVE_VL_INHERIT flag, and the deferred vector
141   if set indicates that the thread is in streaming mode and the vector length
142   and register data (if present) describe the streaming SVE data and vector
146   the thread's vector length (in sve_context.vl).
185 * The vector length cannot be changed via signal return.  If sve_context.vl in
186   the signal frame does not match the current vector length, the signal return
192   vector length in the new mode.
198 Some new prctl() calls are added to allow programs to manage the SVE vector
203     Sets the vector length of the calling thread and related flags, where
206     vl is the desired vector length, where sve_vl_valid(vl) must be true.
212 	    Inherit the current vector length across execve().  Otherwise, the
213 	    vector length is reset to the system default at execve().  (See
218 	    Defer the requested vector length change until the next execve()
226 	    This allows launching of a new program with a different vector
235 	EINVAL: SVE not supported, invalid vector length requested, or
241     * Either the calling thread's vector length or the deferred vector length
248     * Any previously outstanding deferred vector length change in the calling
252       PR_SVE_GET_VL.  The vector length reported in this value is the new
253       current vector length for this thread if PR_SVE_SET_VL_ONEXEC was not
254       present in arg; otherwise, the reported vector length is the deferred
255       vector length that will be applied at the next execve() by the calling
258     * Changing the vector length causes all of P0..P15, FFR and all bits of
261       vector length, or calling PR_SVE_SET_VL with the PR_SVE_SET_VL_ONEXEC
262       flag, does not constitute a change to the vector length for this purpose.
267     Gets the vector length of the calling thread.
273 	    Vector length will be inherited across execve().
276     vector length change (which would only normally be the case between a
279     To extract the vector length from the result, bitwise and it with
315 	thread changes its vector length etc.
319 	Target thread's current vector length, in bytes.
323 	Maximum possible vector length for the target thread.
365 * The effects of changing the vector length and/or flags are equivalent to
377   case only the vector length and flags are changed (along with any
391   for the vector length actually set.  The thread's FPSIMD state is
421   to set the default vector length for userspace processes:
426     default vector length to the specified value rounded to a supported value
427     using the same rules as for setting vector length via PR_SVE_SET_VL.
432     At boot, the default vector length is initially set to 64 or the maximum
433     supported vector length, whichever is smaller.  This determines the initial
434     vector length of the init process (PID 1).
436     Reading this file returns the current system default vector length.
438 * At every execve() call, the new vector length of the new process is set to
439   the system default vector length, unless
444     * a deferred vector length change is pending, established via the
447 * Modifying the system default vector length does not affect the vector length
453 * The arm64 specific DWARF standard [5] added the VG (Vector Granule) register
457 * Its value is equivalent to the current SVE vector length (VL) in bits divided
483 * 32 8VL-bit vector registers Z0..Z31
484   For each Zn, Zn bits [127:0] alias the ARMv8-A vector register Vn.
493 * a VL "pseudo-register" that determines the size of each vector register
502 * The maximum vector length is determined by the hardware:
564 * 32 128-bit vector registers V0..V31