arch/arm64/memory.rst

8 Linux kernel. The architecture allows up to 4 levels of translation
9 tables with a 4KB page size and up to 3 levels with a 64KB page size.
11 AArch64 Linux uses either 3 levels or 4 levels of translation tables
12 with the 4KB page configuration, allowing 39-bit (512GB) or 48-bit
14 64KB pages, only 2 levels of translation tables, allowing 42-bit (4TB)
18 only available when running with a 64KB page size and expands the
23 contains only user (non-global) mappings.  The swapper_pg_dir address is
27 AArch64 Linux memory layout with 4KB pages + 4 levels (48-bit)::
30   -----------------------------------------------------------------------
44 AArch64 Linux memory layout with 64KB pages + 3 levels (52-bit with HW support)::
47   -----------------------------------------------------------------------
48   0000000000000000	000fffffffffffff	   4PB		user
49   fff0000000000000	ffff7fffffffffff	  ~4PB		kernel logical memory map
57   fffffc0000000000	ffffffdfffffffff	  ~4TB		vmemmap
61 Translation table lookup with 4KB pages::
63   +--------+--------+--------+--------+--------+--------+--------+--------+
65   +--------+--------+--------+--------+--------+--------+--------+--------+
68             |        |         |         |         |   [11:0]  in-page offset
69             |        |         |         |         +-> [20:12] L3 index
70             |        |         |         +-----------> [29:21] L2 index
71             |        |         +---------------------> [38:30] L1 index
72             |        +-------------------------------> [47:39] L0 index
73             +----------------------------------------> [55] TTBR0/1
76 Translation table lookup with 64KB pages::
78   +--------+--------+--------+--------+--------+--------+--------+--------+
80   +--------+--------+--------+--------+--------+--------+--------+--------+
83             |        |    |               |            [15:0]  in-page offset
84             |        |    |               +----------> [28:16] L3 index
85             |        |    +--------------------------> [41:29] L2 index
86             |        +-------------------------------> [47:42] L1 index (48-bit)
87             |                                          [51:42] L1 index (52-bit)
88             +----------------------------------------> [55] TTBR0/1
95 GICv2 gets mapped next to the HYP idmap page, as do vectors when
101 52-bit VA support in the kernel
102 -------------------------------
103 If the ARMv8.2-LVA optional feature is present, and we are running
104 with a 64KB page size; then it is possible to use 52-bits of address
106 binary that supports 52-bit must also be able to fall back to 48-bit
110 higher addresses such that they are invariant to 48/52-bit VAs. Due
113 kernel VA space for both 48/52-bit. (Switching from 48-bit to 52-bit,
118 is kept constant at 0xFFF0000000000000 (corresponding to 52-bit),
123 As a single binary will need to support both 48-bit and 52-bit VA
124 spaces, the VMEMMAP must be sized large enough for 52-bit VAs and
142 52-bit userspace VAs
143 --------------------
145 VA space maximum size of 48-bits, the kernel will, by default,
146 return virtual addresses to userspace from a 48-bit range.
148 Software can "opt-in" to receiving VAs from a 52-bit space by
149 specifying an mmap hint parameter that is larger than 48-bit.
153 .. code-block:: c
158 from a 52-bit space by enabling the following kernel config options:
160 .. code-block:: sh