arch/arm64/booting.rst

10 is relevant to all public releases of the AArch64 Linux kernel.
13 (EL0 - EL3), with EL0, EL1 and EL2 having a secure and a non-secure
15 level and exists only in secure mode. Both are architecturally optional.
19 is passed to the Linux kernel.  This may include secure monitor and
28 3. Decompress the kernel image
29 4. Call the kernel image
33 ---------------------------
38 kernel will use for volatile data storage in the system.  It performs
39 this in a machine dependent manner.  (It may use internal algorithms
41 the RAM in the machine, or any other method the boot loader designer
46 -------------------------
50 The device tree blob (dtb) must be placed on an 8-byte boundary and must
51 not exceed 2 megabytes in size. Since the dtb will be mapped cacheable
52 using blocks of up to 2 megabytes in size, it must not be placed within
56 the 512 MB region starting at text_offset bytes below the kernel Image.
58 3. Decompress the kernel image
59 ------------------------------
63 The AArch64 kernel does not currently provide a decompressor and
70 4. Call the kernel image
71 ------------------------
75 The decompressed kernel image contains a 64-byte header as follows::
81   u64 flags;			/* kernel flags, little endian */
91 - As of v3.17, all fields are little endian unless stated otherwise.
93 - code0/code1 are responsible for branching to stext.
95 - when booting through EFI, code0/code1 are initially skipped.
100 - Prior to v3.17, the endianness of text_offset was not specified.  In
101   these cases image_size is zero and text_offset is 0x80000 in the
102   endianness of the kernel.  Where image_size is non-zero image_size is
103   little-endian and must be respected.  Where image_size is zero,
106 - The flags field (introduced in v3.17) is a little-endian 64-bit field
110   Bit 0		Kernel endianness.  1 if BE, 0 if LE.
111   Bit 1-2	Kernel Page size.
113 			* 0 - Unspecified.
114 			* 1 - 4K
115 			* 2 - 16K
116 			* 3 - 64K
117   Bit 3		Kernel physical placement
126 			  the 48-bit addressable range of physical memory
127   Bits 4-63	Reserved.
130 - When image_size is zero, a bootloader should attempt to keep as much
131   memory as possible free for use by the kernel immediately after the
132   end of the kernel image. The amount of space required will vary
136 address anywhere in usable system RAM and called there. The region
138 special significance to the kernel, and may be used for other purposes.
140 use by the kernel.
145 If an initrd/initramfs is passed to the kernel at boot, it must reside
146 entirely within a 1 GB aligned physical memory window of up to 32 GB in
147 size that fully covers the kernel Image as well.
149 Any memory described to the kernel (even that below the start of the
150 image) which is not marked as reserved from the kernel (e.g., with a
151 memreserve region in the device tree) will be considered as available to
152 the kernel.
154 Before jumping into the kernel, the following conditions must be met:
156 - Quiesce all DMA capable devices so that memory does not get
160 - Primary CPU general-purpose register settings:
162     - x0 = physical address of device tree blob (dtb) in system RAM.
163     - x1 = 0 (reserved for future use)
164     - x2 = 0 (reserved for future use)
165     - x3 = 0 (reserved for future use)
167 - CPU mode
169   All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError,
171   The CPU must be in non-secure state, either in EL2 (RECOMMENDED in order
172   to have access to the virtualisation extensions), or in EL1.
174 - Caches, MMUs
179   entries corresponding to the loaded kernel image.
181   The address range corresponding to the loaded kernel image must be
182   cleaned to the PoC. In the presence of a system cache or other
190 - Architected timers
194   kernel at EL1, CNTHCTL_EL2 must have EL1PCTEN (bit 0) set where
197 - Coherency
199   All CPUs to be booted by the kernel must be part of the same coherency
200   domain on entry to the kernel.  This may require IMPLEMENTATION DEFINED
204 - System registers
207   level where the kernel image will be entered must be initialised by
208   software at a higher exception level to prevent execution in an UNKNOWN
212   - If EL3 is present:
214     - SCR_EL3.FIQ must have the same value across all CPUs the kernel is
216     - The value of SCR_EL3.FIQ must be the same as the one present at boot
217       time whenever the kernel is executing.
219   - If EL3 is present and the kernel is entered at EL2:
221     - SCR_EL3.HCE (bit 8) must be initialised to 0b1.
223   For systems with a GICv3 interrupt controller to be used in v3 mode:
224   - If EL3 is present:
226       - ICC_SRE_EL3.Enable (bit 3) must be initialised to 0b1.
227       - ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1.
228       - ICC_CTLR_EL3.PMHE (bit 6) must be set to the same value across
229         all CPUs the kernel is executing on, and must stay constant
230         for the lifetime of the kernel.
232   - If the kernel is entered at EL1:
234       - ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1
235       - ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1.
237   - The DT or ACPI tables must describe a GICv3 interrupt controller.
239   For systems with a GICv3 interrupt controller to be used in
242   - If EL3 is present:
246   - If the kernel is entered at EL1:
250   - The DT or ACPI tables must describe a GICv2 interrupt controller.
254   - If EL3 is present:
256     - SCR_EL3.APK (bit 16) must be initialised to 0b1
257     - SCR_EL3.API (bit 17) must be initialised to 0b1
259   - If the kernel is entered at EL1:
261     - HCR_EL2.APK (bit 40) must be initialised to 0b1
262     - HCR_EL2.API (bit 41) must be initialised to 0b1
266   - If EL3 is present:
268     - CPTR_EL3.TAM (bit 30) must be initialised to 0b0
269     - CPTR_EL2.TAM (bit 30) must be initialised to 0b0
270     - AMCNTENSET0_EL0 must be initialised to 0b1111
271     - AMCNTENSET1_EL0 must be initialised to a platform specific value
275   - If the kernel is entered at EL1:
277     - AMCNTENSET0_EL0 must be initialised to 0b1111
278     - AMCNTENSET1_EL0 must be initialised to a platform specific value
284   - If EL3 is present and the kernel is entered at EL2:
286     - SCR_EL3.FGTEn (bit 27) must be initialised to 0b1.
290   - If EL3 is present and the kernel is entered at EL2:
292     - SCR_EL3.HXEn (bit 38) must be initialised to 0b1.
296   - If EL3 is present:
298     - CPTR_EL3.TFP (bit 10) must be initialised to 0b0.
300   - If EL2 is present and the kernel is entered at EL1:
302     - CPTR_EL2.TFP (bit 10) must be initialised to 0b0.
306   - if EL3 is present:
308     - CPTR_EL3.EZ (bit 8) must be initialised to 0b1.
310     - ZCR_EL3.LEN must be initialised to the same value for all CPUs the
311       kernel is executed on.
313   - If the kernel is entered at EL1 and EL2 is present:
315     - CPTR_EL2.TZ (bit 8) must be initialised to 0b0.
317     - CPTR_EL2.ZEN (bits 17:16) must be initialised to 0b11.
319     - ZCR_EL2.LEN must be initialised to the same value for all CPUs the
320       kernel will execute on.
324   - If EL3 is present:
326     - CPTR_EL3.ESM (bit 12) must be initialised to 0b1.
328     - SCR_EL3.EnTP2 (bit 41) must be initialised to 0b1.
330     - SMCR_EL3.LEN must be initialised to the same value for all CPUs the
331       kernel will execute on.
333  - If the kernel is entered at EL1 and EL2 is present:
335     - CPTR_EL2.TSM (bit 12) must be initialised to 0b0.
337     - CPTR_EL2.SMEN (bits 25:24) must be initialised to 0b11.
339     - SCTLR_EL2.EnTP2 (bit 60) must be initialised to 0b1.
341     - SMCR_EL2.LEN must be initialised to the same value for all CPUs the
342       kernel will execute on.
344     - HWFGRTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01.
346     - HWFGWTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01.
348     - HWFGRTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01.
350     - HWFGWTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01.
354   - If EL3 is present:
356     - SMCR_EL3.FA64 (bit 31) must be initialised to 0b1.
358  - If the kernel is entered at EL1 and EL2 is present:
360     - SMCR_EL2.FA64 (bit 31) must be initialised to 0b1.
364   - If EL3 is present:
366     - SCR_EL3.ATA (bit 26) must be initialised to 0b1.
368   - If the kernel is entered at EL1 and EL2 is present:
370     - HCR_EL2.ATA (bit 56) must be initialised to 0b1.
374   - If EL3 is present:
376     - SMCR_EL3.EZT0 (bit 30) must be initialised to 0b1.
378  - If the kernel is entered at EL1 and EL2 is present:
380     - SMCR_EL2.EZT0 (bit 30) must be initialised to 0b1.
384   - If the kernel is entered at EL1 and EL2 is present:
386     - HCRX_EL2.MSCEn (bit 11) must be initialised to 0b1.
390   - If EL3 is present:
392     - SCR_EL3.TCR2En (bit 43) must be initialised to 0b1.
394  - If the kernel is entered at EL1 and EL2 is present:
396     - HCRX_EL2.TCR2En (bit 14) must be initialised to 0b1.
400   - If EL3 is present:
402     - SCR_EL3.PIEn (bit 45) must be initialised to 0b1.
404   - If the kernel is entered at EL1 and EL2 is present:
406     - HFGRTR_EL2.nPIR_EL1 (bit 58) must be initialised to 0b1.
408     - HFGWTR_EL2.nPIR_EL1 (bit 58) must be initialised to 0b1.
410     - HFGRTR_EL2.nPIRE0_EL1 (bit 57) must be initialised to 0b1.
412     - HFGRWR_EL2.nPIRE0_EL1 (bit 57) must be initialised to 0b1.
416 enter the kernel in the same exception level.  Where the values documented
421 The boot loader is expected to enter the kernel on each CPU in the
424 - The primary CPU must jump directly to the first instruction of the
425   kernel image.  The device tree blob passed by this CPU must contain
426   an 'enable-method' property for each cpu node.  The supported
427   enable-methods are described below.
430   properties and insert them into the blob prior to kernel entry.
432 - CPUs with a "spin-table" enable-method must have a 'cpu-release-addr'
433   property in their cpu node.  This property identifies a
434   naturally-aligned 64-bit zero-initalised memory location.
436   These CPUs should spin outside of the kernel in a reserved area of
437   memory (communicated to the kernel by a /memreserve/ region in the
438   device tree) polling their cpu-release-addr location, which must be
439   contained in the reserved region.  A wfe instruction may be inserted
440   to reduce the overhead of the busy-loop and a sev will be issued by
442   cpu-release-addr returns a non-zero value, the CPU must jump to this
443   value.  The value will be written as a single 64-bit little-endian
447 - CPUs with a "psci" enable method should remain outside of
448   the kernel (i.e. outside of the regions of memory described to the
449   kernel in the memory node, or in a reserved area of memory described
450   to the kernel by a /memreserve/ region in the device tree).  The
451   kernel will issue CPU_ON calls as described in ARM document number ARM
453   processors") to bring CPUs into the kernel.
455   The device tree should contain a 'psci' node, as described in
458 - Secondary CPU general-purpose register settings
460   - x0 = 0 (reserved for future use)
461   - x1 = 0 (reserved for future use)
462   - x2 = 0 (reserved for future use)
463   - x3 = 0 (reserved for future use)