arch/arm64/booting.rst

12 The AArch64 exception model is made up of a number of exception levels
13 (EL0 - EL3), with EL0, EL1 and EL2 having a secure and a non-secure
20 hypervisor code, or it may just be a handful of instructions for
21 preparing a minimal boot environment.
23 Essentially, the boot loader should provide (as a minimum) the
39 this in a machine dependent manner.  (It may use internal algorithms
63 The AArch64 kernel does not currently provide a decompressor and
65 loader if a compressed Image target (e.g. Image.gz) is used.  For
75 The decompressed kernel image contains a 64-byte header as follows::
106 - The flags field (introduced in v3.17) is a little-endian 64-bit field
130 - When image_size is zero, a bootloader should attempt to keep as much
135 The Image must be placed text_offset bytes from a 2MB aligned base
146 entirely within a 1 GB aligned physical memory window of up to 32 GB in
150 image) which is not marked as reserved from the kernel (e.g., with a
182   cleaned to the PoC. In the presence of a system cache or other
193   be programmed with a consistent value on all CPUs.  If entering the
208   software at a higher exception level to prevent execution in an UNKNOWN
223   For systems with a GICv3 interrupt controller to be used in v3 mode:
237   - The DT or ACPI tables must describe a GICv3 interrupt controller.
239   For systems with a GICv3 interrupt controller to be used in
250   - The DT or ACPI tables must describe a GICv2 interrupt controller.
271     - AMCNTENSET1_EL0 must be initialised to a platform specific value
278     - AMCNTENSET1_EL0 must be initialised to a platform specific value
432 - CPUs with a "spin-table" enable-method must have a 'cpu-release-addr'
433   property in their cpu node.  This property identifies a
436   These CPUs should spin outside of the kernel in a reserved area of
437   memory (communicated to the kernel by a /memreserve/ region in the
439   contained in the reserved region.  A wfe instruction may be inserted
440   to reduce the overhead of the busy-loop and a sev will be issued by
441   the primary CPU.  When a read of the location pointed to by the
442   cpu-release-addr returns a non-zero value, the CPU must jump to this
443   value.  The value will be written as a single 64-bit little-endian
447 - CPUs with a "psci" enable method should remain outside of
449   kernel in the memory node, or in a reserved area of memory described
450   to the kernel by a /memreserve/ region in the device tree).  The
452   DEN 0022A ("Power State Coordination Interface System Software on ARM
455   The device tree should contain a 'psci' node, as described in