arch/arm64/amu.rst

9 Date: 2019-09-10
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24 optional external memory-mapped interface.
27 of four fixed and architecturally defined 64-bit event counters.
29   - CPU cycle counter: increments at the frequency of the CPU.
30   - Constant counter: increments at the fixed frequency of the system
32   - Instructions retired: increments with every architecturally executed
34   - Memory stall cycles: counts instruction dispatch stall cycles caused by
44 64-bit event counters.
50 -------------
61 Firmware (code running at higher exception levels, e.g. arm-tf) support is
64  - Enable access for lower exception levels (EL2 and EL1) to the AMU
66  - Enable the counters. If not enabled these will read as 0.
67  - Save/restore the counters before/after the CPU is being put/brought up
86  - SYS_AMEVCNTR0_CORE_EL0
87  - SYS_AMEVCNTR0_CONST_EL0
88  - SYS_AMEVCNTR0_INST_RET_EL0
89  - SYS_AMEVCNTR0_MEM_STALL_EL0
98 ----------------
102  - Security reasons: they might expose information about code executed in
104  - Purpose: AMU counters are intended for system management use.
110 --------------
115  - Security reasons: they might expose information about code executed