Lines Matching +full:data +full:- +full:transfer
1 .. SPDX-License-Identifier: GPL-2.0
4 STM32 DMA-MDMA chaining
9 ------------
11 This document describes the STM32 DMA-MDMA chaining feature. But before going
14 To offload data transfers from the CPU, STM32 microprocessors (MPUs) embed
28 STM32 DMA is mainly used to implement central data buffer storage (usually in
30 without the ability to generate convenient burst transfer ensuring the best
35 STM32 MDMA (Master DMA) is mainly used to manage direct data transfers between
36 RAM data buffers without CPU intervention. It can also be used in a
37 hierarchical structure that uses STM32 DMA as first level data buffer
44 ----------
46 STM32 DMA-MDMA chaining feature relies on the strengths of STM32 DMA and
50 (when DMA data counter - DMA_SxNDTR - reaches 0), the memory pointers
51 (configured with DMA_SxSM0AR and DMA_SxM1AR) are swapped and the DMA data
54 the STM32 DMA transfer.
56 With STM32 MDMA linked-list mode, a single request initiates the data array
57 (collection of nodes) to be transferred until the linked-list pointer for the
58 channel is null. The channel transfer complete of the last node is the end of
59 transfer, unless first and last nodes are linked to each other, in such a
60 case, the linked-list loops on to create a circular MDMA transfer.
64 resources and bus congestion. Transfer Complete signal of STM32 DMA channel
65 can triggers STM32 MDMA transfer. STM32 MDMA can clear the request generated
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73 | channels | channels | Transfer | request |
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110 STM32 DMA-MDMA chaining feature then uses a SRAM buffer. STM32MP1 SoCs embed
111 three fast access static internal RAMs of various size, used for data storage.
119 dma[1:2]-tcf[0:7]
120 .----------------.
123 |------------| | / \ | |------------|
124 | DMA_SxM0AR |<=>| | SRAM | |<=>| []-[]...[] |
128 STM32 DMA-MDMA chaining uses (struct dma_slave_config).peripheral_config to
133 * the address of the STM32 DMA register to clear the Transfer Complete
135 * the mask of the Transfer Complete interrupt flag of the STM32 DMA channel.
137 Device Tree updates for STM32 DMA-MDMA chaining support
138 -------------------------------------------------------
147 my_foo_device_dma_pool: dma-sram@0 {
156 If the SRAM period is greater than the expected DMA transfer, then STM32 DMA
197 destination address increment, block transfer with 128 bytes per single
198 transfer
207 Transfer Complete flag passed through
210 Driver updates for STM32 DMA-MDMA chaining support in foo driver
211 ----------------------------------------------------------------
217 STM32 DMA transfer (where memory address targets now the SRAM buffer instead
218 of DDR buffer) and one for STM32 MDMA transfer (where memory address targets
254 s->dma_address = sram_buf;
260 s->dma_address += sram_period;
276 len -= bytes;
294 the memory address (depending on the transfer direction) must point on your
302 channel Transfer Complete flag mask.
306 (depending on the transfer direction) must point on your SRAM buffer, and
329 mdma_conf.peripheral_size = dma_conf.peripheral_size; // <- dma_conf
330 mdma_conf.peripheral_config = dma_config.peripheral_config; // <- dma_conf
352 or, depending on the transfer direction, either the original DDR buffer (in
359 descriptor you want a callback to be called at the end of the transfer
362 the overall transfer:
371 As STM32 MDMA channel transfer is triggered by STM32 DMA, you must issue
375 transfer or the period completion.
378 cyclic Double-Buffer mode so it won't be disabled by HW, you need to terminate
379 it. STM32 MDMA channel will be stopped by HW in case of sg transfer, but not
380 in case of cyclic transfer. You can terminate it whatever the kind of transfer.
382 **STM32 DMA-MDMA chaining DMA_MEM_TO_DEV special case**
384 STM32 DMA-MDMA chaining in DMA_MEM_TO_DEV is a special case. Indeed, the
385 STM32 MDMA feeds the SRAM buffer with the DDR data, and the STM32 DMA reads
386 data from SRAM buffer. So some data (the first period) have to be copied in
389 A trick could be pausing the STM32 DMA channel (that will raise a Transfer
390 Complete signal, triggering the STM32 MDMA channel), but the first data read
393 "removed" from the sg or the cyclic transfer.
395 Due to this complexity, rather use the STM32 DMA-MDMA chaining for
400 ---------
408 .. _STM32MP1: https://www.st.com/en/microcontrollers-microprocessors/stm32mp1-series.html
409 …24: https://www.st.com/resource/en/application_note/an5224-stm32-dmamux-the-dma-request-router-stm…
410 …st.com/resource/en/application_note/dm00046011-using-the-stm32f2-stm32f4-and-stm32f7-series-dma-co…
411 …s://www.st.com/resource/en/application_note/an5001-stm32cube-expansion-package-for-stm32h7-series-…
415 - Amelie Delaunay <amelie.delaunay@foss.st.com>