Lines Matching +full:channel +full:- +full:use
1 .. SPDX-License-Identifier: GPL-2.0
4 STM32 DMA-MDMA chaining
9 ------------
11 This document describes the STM32 DMA-MDMA chaining feature. But before going
44 ----------
46 STM32 DMA-MDMA chaining feature relies on the strengths of STM32 DMA and
50 (when DMA data counter - DMA_SxNDTR - reaches 0), the memory pointers
56 With STM32 MDMA linked-list mode, a single request initiates the data array
57 (collection of nodes) to be transferred until the linked-list pointer for the
58 channel is null. The channel transfer complete of the last node is the end of
60 case, the linked-list loops on to create a circular MDMA transfer.
64 resources and bus congestion. Transfer Complete signal of STM32 DMA channel
71 +--------------+----------------+-----------+------------+
77 | Channel *0* | DMA1 channel 0 | dma1_tcf0 | *0x00* |
78 +--------------+----------------+-----------+------------+
79 | Channel *1* | DMA1 channel 1 | dma1_tcf1 | *0x01* |
80 +--------------+----------------+-----------+------------+
81 | Channel *2* | DMA1 channel 2 | dma1_tcf2 | *0x02* |
82 +--------------+----------------+-----------+------------+
83 | Channel *3* | DMA1 channel 3 | dma1_tcf3 | *0x03* |
84 +--------------+----------------+-----------+------------+
85 | Channel *4* | DMA1 channel 4 | dma1_tcf4 | *0x04* |
86 +--------------+----------------+-----------+------------+
87 | Channel *5* | DMA1 channel 5 | dma1_tcf5 | *0x05* |
88 +--------------+----------------+-----------+------------+
89 | Channel *6* | DMA1 channel 6 | dma1_tcf6 | *0x06* |
90 +--------------+----------------+-----------+------------+
91 | Channel *7* | DMA1 channel 7 | dma1_tcf7 | *0x07* |
92 +--------------+----------------+-----------+------------+
93 | Channel *8* | DMA2 channel 0 | dma2_tcf0 | *0x08* |
94 +--------------+----------------+-----------+------------+
95 | Channel *9* | DMA2 channel 1 | dma2_tcf1 | *0x09* |
96 +--------------+----------------+-----------+------------+
97 | Channel *10* | DMA2 channel 2 | dma2_tcf2 | *0x0A* |
98 +--------------+----------------+-----------+------------+
99 | Channel *11* | DMA2 channel 3 | dma2_tcf3 | *0x0B* |
100 +--------------+----------------+-----------+------------+
101 | Channel *12* | DMA2 channel 4 | dma2_tcf4 | *0x0C* |
102 +--------------+----------------+-----------+------------+
103 | Channel *13* | DMA2 channel 5 | dma2_tcf5 | *0x0D* |
104 +--------------+----------------+-----------+------------+
105 | Channel *14* | DMA2 channel 6 | dma2_tcf6 | *0x0E* |
106 +--------------+----------------+-----------+------------+
107 | Channel *15* | DMA2 channel 7 | dma2_tcf7 | *0x0F* |
108 +--------------+----------------+-----------+------------+
110 STM32 DMA-MDMA chaining feature then uses a SRAM buffer. STM32MP1 SoCs embed
119 dma[1:2]-tcf[0:7]
120 .----------------.
123 |------------| | / \ | |------------|
124 | DMA_SxM0AR |<=>| | SRAM | |<=>| []-[]...[] |
128 STM32 DMA-MDMA chaining uses (struct dma_slave_config).peripheral_config to
132 * the STM32 MDMA request (which is actually the DMAMUX channel ID),
135 * the mask of the Transfer Complete interrupt flag of the STM32 DMA channel.
137 Device Tree updates for STM32 DMA-MDMA chaining support
138 -------------------------------------------------------
147 my_foo_device_dma_pool: dma-sram@0 {
171 **2. Allocate a STM32 DMA channel and a STM32 MDMA channel**
173 You need to define an extra channel in your device tree node, in addition to
176 This new channel must be taken from STM32 MDMA channels, so, the phandle of
177 the DMA controller to use is the MDMA controller's one.
183 dmas = <&dmamux1 ...>, // STM32 DMA channel
184 <&mdma1 0 0x3 0x1200000a 0 0>; // + STM32 MDMA channel
190 by MDMA driver with the STM32 DMAMUX channel ID passed through
193 2. The priority level : choose Very High (0x3) so that your channel will
196 3. A 32bit mask specifying the DMA channel configuration : source and
201 request: it will be overwritten by MDMA driver, with the DMA channel
206 request: it will be overwritten by MDMA driver, with the DMA channel
210 Driver updates for STM32 DMA-MDMA chaining support in foo driver
211 ----------------------------------------------------------------
245 /* Create sg table for STM32 DMA channel */
254 s->dma_address = sram_buf;
260 s->dma_address += sram_period;
263 /* Create sg table for STM32 MDMA channel */
276 len -= bytes;
292 First, use dmaengine_slave_config() with a struct dma_slave_config to
293 configure STM32 DMA channel. You just have to take care of DMA addresses,
300 three u32 : the first one containing STM32 DMAMUX channel ID, the second one
301 the channel interrupt flag clear register address, and the third one the
302 channel Transfer Complete flag mask.
304 Then, use dmaengine_slave_config with another struct dma_slave_config to
305 configure STM32 MDMA channel. Take care of DMA addresses, the device address
308 DMA operation. Use the previous (struct dma_slave_config).peripheral_size
311 struct dma_slave_config to configure STM32 MDMA channel.
329 mdma_conf.peripheral_size = dma_conf.peripheral_size; // <- dma_conf
330 mdma_conf.peripheral_config = dma_config.peripheral_config; // <- dma_conf
334 **2. Get a descriptor for STM32 DMA channel transaction**
342 **3. Get a descriptor for STM32 MDMA channel transaction**
346 * dmaengine_prep_slave_sg(), then use dmaengine_prep_slave_sg() for
348 * dmaengine_prep_dma_cyclic(), then use dmaengine_prep_dma_cyclic() for
351 Use the new sg_list using SRAM buffer (in case of dmaengine_prep_slave_sg())
371 As STM32 MDMA channel transfer is triggered by STM32 DMA, you must issue
372 STM32 MDMA channel before STM32 DMA channel.
377 Don't forget to terminate both channels. STM32 DMA channel is configured in
378 cyclic Double-Buffer mode so it won't be disabled by HW, you need to terminate
379 it. STM32 MDMA channel will be stopped by HW in case of sg transfer, but not
382 **STM32 DMA-MDMA chaining DMA_MEM_TO_DEV special case**
384 STM32 DMA-MDMA chaining in DMA_MEM_TO_DEV is a special case. Indeed, the
389 A trick could be pausing the STM32 DMA channel (that will raise a Transfer
390 Complete signal, triggering the STM32 MDMA channel), but the first data read
395 Due to this complexity, rather use the STM32 DMA-MDMA chaining for
400 ---------
408 .. _STM32MP1: https://www.st.com/en/microcontrollers-microprocessors/stm32mp1-series.html
409 …24: https://www.st.com/resource/en/application_note/an5224-stm32-dmamux-the-dma-request-router-stm…
410 …st.com/resource/en/application_note/dm00046011-using-the-stm32f2-stm32f4-and-stm32f7-series-dma-co…
411 …s://www.st.com/resource/en/application_note/an5001-stm32cube-expansion-package-for-stm32h7-series-…
415 - Amelie Delaunay <amelie.delaunay@foss.st.com>