arch/arm/cluster-pm-race-avoidance.rst

2 Cluster-wide Power-up/power-down race avoidance algorithm
16 ---------
20 power consumption and thermal dissipation.
29 cluster-level operations are only performed when it is truly safe to do
34 are not immediately enabled when a cluster powers up.  Since enabling or
35 disabling those mechanisms may itself be a non-atomic operation (such as
38 power-down and power-up at the cluster level.
46 -----------
50 	- DOWN
51 	- COMING_UP
52 	- UP
53 	- GOING_DOWN
57 	    +---------> UP ----------+
63 	    +--------- DOWN <--------+
71 	The CPU or cluster has committed to moving to the UP state.
75 UP:
92 CPUs in the cluster simultaneously modifying the state.  The cluster-
101 ---------
103 In this algorithm, each individual core in a multi-core processor is
104 referred to as a "CPU".  CPUs are assumed to be single-threaded:
111 	- CPU_DOWN
112 	- CPU_COMING_UP
113 	- CPU_UP
114 	- CPU_GOING_DOWN
120 	      +-----------> CPU_UP ------------+
126 	      +----------- CPU_DOWN <----------+
143 	power-down.  On reaching this state, the CPU will typically
144 	power itself down or suspend itself, via a WFI instruction or a
153 		a) an explicit hardware power-up operation, resulting
161 	cluster is set up and coherent.  If the cluster is not ready,
163 	cluster has been set up.
214 -------------
219 CPU can start up while another CPU is tearing the cluster down.
223 view of the cluster state as seen by a CPU setting the CPU up.
226 that a CPU which is setting up the cluster can advertise its state
233 		- CLUSTER_DOWN
234 		- CLUSTER_UP
235 		- CLUSTER_GOING_DOWN
239 		- INBOUND_NOT_COMING_UP
240 		- INBOUND_COMING_UP
247 	          +==========> INBOUND_NOT_COMING_UP -------------+
250 	     CLUSTER_UP     <----+                                |
257 	  INBOUND_COMING_UP <----+                                |
260 	          +===========     CLUSTER_DOWN      <------------+
263 	Transitions -----> can only be made by the outbound CPU, and
287 	CLUSTER_UP/INBOUND_COMING_UP is equivalent to UP in the basic
309 		a) an explicit hardware power-up operation, resulting
317 	In this state, an inbound CPU sets up the cluster, including
322 	The purpose of this state is to do sufficient cluster-level
329 		cluster-level setup and hardware coherency complete
336 	Cluster-level setup is complete and hardware coherency is
354 	Cluster-level setup is complete and hardware coherency is
359 	made to power the cluster down.
366 		policy decision to power down the cluster
377 	cluster-level coherency.
389 			cluster torn down and ready to power off
398 			a) an explicit hardware power-up operation,
408 	come online in the meantime and is trying to set up the cluster
418 		   set up the cluster again from there.
429 				cluster-level setup and hardware
437 			cluster torn down and ready to power off
444 --------------------------------
446 The CPU which performs cluster tear-down operations on the outbound side
461 non-coherent.
466 Because CPUs may power up asynchronously in response to external wake-up
468 attempts to play the first man role and do the cluster-level
472 Cluster-level initialisation may involve actions such as configuring
481 ------------------------
485 	The current ARM-based implementation is split between
486 	arch/arm/common/mcpm_head.S (low-level inbound CPU operations) and
496 	low-level power-up code in mcpm_head.S.  This could
497 	involve CPU-specific setup code, but in the current
503 	the case of an aborted cluster power-down).
506 	functions due to the extra inter-CPU coordination which
510 	the low-level power-up code in mcpm_head.S.  This
511 	typically involves platform-specific setup code,
512 	provided by the platform-specific power_up_setup
520 	extended by replicating the cluster-level states for the
522 	rules for the intermediate (non-outermost) cluster levels.
526 --------
531 Copyright (C) 2012-2013  Linaro Limited