admin-guide/perf/hisi-pcie-pmu.rst

2 HiSilicon PCIe Performance Monitoring Unit (PMU)
5 On Hip09, HiSilicon PCIe Performance Monitoring Unit (PMU) could monitor
6 bandwidth, latency, bus utilization and buffer occupancy data of PCIe.
8 Each PCIe Core has a PMU to monitor multi Root Ports of this PCIe Core and
12 HiSilicon PCIe PMU driver
15 The PCIe PMU driver registers a perf PMU with the name of its sicl-id and PCIe
40   ------------------------------------------
42   $# perf stat -e hisi_pcie0_core0/rx_mwr_latency,port=0xffff/
43   $# perf stat -e hisi_pcie0_core0/rx_mwr_cnt,port=0xffff/
56 …$# perf stat -e "{hisi_pcie0_core0/rx_mwr_latency,port=0xffff/,hisi_pcie0_core0/rx_mwr_cnt,port=0x…
59 Also attach to a task is unsupported for PCIe PMU.
62 --------------
67    Ports or downstream target Endpoint. PCIe PMU driver support "port" and
75    - port
77      "port" filter can be used in all PCIe PMU events, target Root Port can be
78      selected by configuring the 16-bits-bitmap "port". Multi ports can be
79      selected for AP-layer-events, and only one port can be selected for
80      TL/DL-layer-events.
89        $# perf stat -e hisi_pcie0_core0/rx_mwr_latency,port=0x1/ sleep 5
91    - bdf
101        $# perf stat -e hisi_pcie0_core0/rx_mrd_flux,bdf=0x3900/ sleep 5
116      $# perf stat -e hisi_pcie0_core0/rx_mrd_flux,port=0xffff,trig_len=0x4,trig_mode=1/ sleep 5
130      $# perf stat -e hisi_pcie0_core0/rx_mrd_flux,port=0xffff,thr_len=0x4,thr_mode=1/ sleep 5
137    - 2'b00: Reserved (Do not use this since the behaviour is undefined)
138    - 2'b01: Bandwidth of TLP payloads
139    - 2'b10: Bandwidth of TLP headers
140    - 2'b11: Bandwidth of both TLP payloads and headers
148      $# perf stat -e hisi_pcie0_core0/rx_mrd_flux,port=0xffff,len_mode=0x1/ sleep 5