Lines Matching +full:numbering +full:- +full:space

21  +------------------+     +------------------+
22  | Compute Node 0   +-----+ Compute Node 1   |
24  +--------+---------+     +--------+---------+
26  +--------+---------+     +--------+---------+
28  +------------------+     +--------+---------+
36 performance when accessing a given memory target. Each initiator-target
48 	# symlinks -v /sys/devices/system/node/nodeX/access0/targets/
49 	relative: /sys/devices/system/node/nodeX/access0/targets/nodeY -> ../../nodeY
51 	# symlinks -v /sys/devices/system/node/nodeY/access0/initiators/
52 	relative: /sys/devices/system/node/nodeY/access0/initiators/nodeX -> ../../nodeX
82 	# tree -P "read*|write*" /sys/devices/system/node/nodeY/access0/initiators/
84 	|-- read_bandwidth
85 	|-- read_latency
86 	|-- write_bandwidth
87 	`-- write_latency
103 performance characteristics in order to provide large address space of
115 This numbering is different than CPU caches where the cache level (ex:
116 L1, L2, L3) uses the CPU-side view where each increased level is lower
121 The memory-side caches are not directly addressable by software. When
140 a memory-side cache, or that information is not accessible to the kernel.
155 	|-- index1
156 	|   |-- indexing
157 	|   |-- line_size
158 	|   |-- size
159 	|   `-- write_policy
161 The "indexing" will be 0 if it is a direct-mapped cache, and non-zero
162 for any other indexed based, multi-way associativity.
169 The "write_policy" will be 0 for write-back, and non-zero for
170 write-through caching.
176 - Section 5.2.27