Lines Matching full:signal

59     Mapping of the incoming bits in the signal to the colour bits of the pixels.
77     pixel clock is running and the DE signal is moving.
118     If the incoming video signal does not contain synchronization VSYNC and
121     (pixels with deasserted Data Enable signal) are necessary to generate the
125     If the incoming video signal does not contain synchronization VSYNC and
128     (pixels with deasserted Data Enable signal) are necessary to generate the
142     Width of the HSYNC signal in PCLK clock ticks.
148     Width of the VSYNC signal in PCLK clock ticks.
154     Number of PCLK pulses between deassertion of the HSYNC signal and the first
162     line (marked by DE=1) and assertion of the HSYNC signal.
168     Number of video lines between deassertion of the VSYNC signal and the video
176     by DE=1) and assertion of the VSYNC signal.
230     Output video signal frame rate limit in frames per second. Due to
233     Using this parameter one can limit the frame rate by "crippling" the signal
235     the signal appears like having the exact frame rate to the connected display.
239     HSYNC signal polarity.
245     VSYNC signal polarity.
251     DE signal polarity.
267     Width of the HSYNC signal in pixels. The default value is 40.
270     Width of the VSYNC signal in video lines. The default value is 20.
273     Number of PCLK pulses between deassertion of the HSYNC signal and the first
278     line (marked by DE=1) and assertion of the HSYNC signal. The default value
282     Number of video lines between deassertion of the VSYNC signal and the video
287     by DE=1) and assertion of the VSYNC signal. The default value is 30.
352 signal level status capability. The following scan elements are available:
365 The iio device can operate either in "raw" mode where you can fetch the signal
367 In the triggered buffer mode you can follow the signal level changes (activity