Lines Matching refs:RET

13 AMD CPUs predict RET instructions using a Return Address Predictor (aka
17 to predict the target of a subsequent RET instruction.
22 control the speculative target of a subsequent kernel RET, potentially
58  * 'Vulnerable: Safe RET, no microcode':
60    The "Safe RET" mitigation (see below) has been applied to protect the
64  * 'Vulnerable: Microcode, no safe RET':
85  * 'Mitigation: Safe RET':
95    Similar protection as "safe RET" above but employs an IBPB barrier on
123 default one is 'Mitigation: safe RET' which should take care of most
132 As one can surmise, 'Mitigation: safe RET' does come at the cost of some
142 Mitigation: Safe RET
145 The mitigation works by ensuring all RET instructions speculate to
162 Checking the safe RET mitigation actually works
165 In case one wants to validate whether the SRSO safe RET mitigation works
168 * PMC_0xc8 - Count of RET/RET lw retired
169 * PMC_0xc9 - Count of RET/RET lw retired mispredicted
193 should give the same amount. I.e., every RET retired should be