Lines Matching +full:1 +full:c0

9 transitions out of C0 state, the other sibling thread could use return target
10 predictions from the sibling thread that transitioned out of C0.
15 transitioning out of C0. This could result in a guest-controlled return target
38 Affected SMT-capable processors support 1T and 2T modes of execution when SMT
40 processor core to enter 1T mode, it is required that one of the threads
41 requests to transition out of the C0 state. This can be communicated with the
42 HLT instruction or with an MWAIT instruction that requests non-C0.
43 When the thread re-enters the C0 state, the processor transitions back
44 to 2T mode, assuming the other thread is also still in C0 state.
48 16-entry RAP, but in 1T mode, the active thread uses a 32-entry RAP. Upon
49 transition between 1T/2T mode, the RAP contents are not modified but the RAP
52 used by RET predictions in the sibling thread following a 1T/2T switch. In
53 particular, a RET instruction executed immediately after a transition to 1T may
62 instructions with targeted return locations and then transitioning out of C0
86 attempts to transition out of C0. A VMM can use the KVM_CAP_X86_DISABLE_EXITS
91 using the boolean module parameter mitigate_smt_rsb, e.g. ``kvm.mitigate_smt_rsb=1``.