accel/qaic/aic100.rst

1 .. SPDX-License-Identifier: GPL-2.0-only
10 The Qualcomm Cloud AI 100/AIC100 family of products (including SA9000P - part of
16 (x8). An individual SoC on a card can have up to 16 NSPs for running workloads.
20 performance. AIC100 cards are multi-user capable and able to execute workloads
26 An AIC100 card consists of an AIC100 SoC, on-card DDR, and a set of misc
39 AIC100 implements MSI but does not implement MSI-X. AIC100 prefers 17 MSIs to
44 hardware. AIC100 provides 3, 64-bit BARs.
52   configuration, but defaults to 64K. This BAR currently has no purpose.
54 From the host perspective, AIC100 has several key hardware components -
63 ---
71 ---
74 firmware of the card and performs on-card management tasks. It also
79 ---
90 ----------
100 ---
102 AIC100 has on-card DDR. In total, an AIC100 can have up to 32 GB of DDR.
108 High-level Use Flow
111 AIC100 is a multi-user, programmable accelerator typically used for running
125 5. Once the workload is no longer required, make a request to the QSM to
127 6. Once the workload and related artifacts are no longer needed for future
137 When AIC100 is first powered on, it begins executing PBL (Primary Bootloader)
138 from ROM. PBL enumerates the PCIe link, and initializes the BHI (Boot Host
141 Using BHI, the host points PBL to the location of the SBL (Secondary Bootloader)
142 image. The PBL pulls the image from the host, validates it, and begins
148 * SBL initializes the majority of hardware (anything PBL left uninitialized),
166 --------
169 https://github.com/quic/software-kit-for-qualcomm-cloud-ai-100-cc
172 ---------------------
175 https://github.com/quic/software-kit-for-qualcomm-cloud-ai-100
178 -------------
189 +----------------+---------+----------+----------------------------------------+
194 +----------------+---------+----------+----------------------------------------+
197 +----------------+---------+----------+----------------------------------------+
200 +----------------+---------+----------+----------------------------------------+
204 +----------------+---------+----------+----------------------------------------+
206 +----------------+---------+----------+----------------------------------------+
211 +----------------+---------+----------+----------------------------------------+
214 +----------------+---------+----------+----------------------------------------+
218 +----------------+---------+----------+----------------------------------------+
221 +----------------+---------+----------+----------------------------------------+
223 +----------------+---------+----------+----------------------------------------+
227 +----------------+---------+----------+----------------------------------------+
231 +----------------+---------+----------+----------------------------------------+
237 --------
254 * Response FIFO head pointer (offset 0x8). Read/write by the host. Indicates
274 ------------
278 .. code-block:: c
322 	* Bits(1:0) indicate the type of transfer. No transfer(0), to device(1),
343 	* Bits(1:0) contain the encoding of the doorbell length. 0 is 32-bit,
344 	  1 is 16-bit, 2 is 8-bit, 3 is reserved. The doorbell address
355 	* Bit(30) is the to-device DMA fence. Block this request until all
356 	  to-device DMA transfers are complete.
357 	* Bit(29) is the from-device DMA fence. Block this request until all
358 	  from-device DMA transfers are complete.
390 -------------
395 .. code-block:: c
406 	status of this request. 0 is success. Non-zero is an error.
411 from empty to non-empty (unless force MSI is enabled and triggered). In
427 aligned. Since there are 64-bit elements in some NNC messages, 64-bit alignment
437 ------------------------
489 multi-stage recovery process is then used to cleanup both sides, and get the
494 remain in on-card DDR, but the host will need to re-activate the workload if