accel/qaic/aic100.rst

1 .. SPDX-License-Identifier: GPL-2.0-only
10 The Qualcomm Cloud AI 100/AIC100 family of products (including SA9000P - part of
20 performance. AIC100 cards are multi-user capable and able to execute workloads
26 An AIC100 card consists of an AIC100 SoC, on-card DDR, and a set of misc
30 or a Dual M.2 card. Both use PCIe to connect to the host system.
33 DeviceID(DID) combination to uniquely identify itself to the host. AIC100
39 AIC100 implements MSI but does not implement MSI-X. AIC100 prefers 17 MSIs to
43 As a PCIe device, AIC100 utilizes BARs to provide host interfaces to the device
44 hardware. AIC100 provides 3, 64-bit BARs.
46 * The first BAR is 4K in size, and exposes the MHI interface to the host.
49   host.
54 From the host perspective, AIC100 has several key hardware components -
56 * MHI (Modem Host Interface)
63 ---
66 Documentation/mhi/index.rst MHI is the mechanism the host uses to communicate
71 ---
74 firmware of the card and performs on-card management tasks. It also
75 communicates with the host via MHI. Each AIC100 has one of
79 ---
83 (Q6) DSP with HVX and HMX. Each NSP can only run one workload at a time, but
84 multiple NSPs may be assigned to a single workload. Since each NSP can only run
86 "scheduling" is under the purview of the host. AIC100 does not automatically
90 ----------
96 hardware registers to manage the FIFOs (head/tail pointers), but requires host
100 ---
102 AIC100 has on-card DDR. In total, an AIC100 can have up to 32 GB of DDR.
105 the QSM. The host does not have direct access to the DDR, and must make
108 High-level Use Flow
111 AIC100 is a multi-user, programmable accelerator typically used for running
138 from ROM. PBL enumerates the PCIe link, and initializes the BHI (Boot Host
141 Using BHI, the host points PBL to the location of the SBL (Secondary Bootloader)
142 image. The PBL pulls the image from the host, validates it, and begins
145 SBL initializes MHI, and uses MHI to notify the host that the device has entered
150 * SBL offloads the bootlog to the host.
151 * SBL synchronizes timestamps with the host for future logging.
153   host.
158 The QSM uses MHI to notify the host that the device has entered the QSM stage
166 --------
169 https://github.com/quic/software-kit-for-qualcomm-cloud-ai-100-cc
172 ---------------------
175 https://github.com/quic/software-kit-for-qualcomm-cloud-ai-100
178 -------------
189 +----------------+---------+----------+----------------------------------------+
193 |                |         |          | channel is sent back to the host.      |
194 +----------------+---------+----------+----------------------------------------+
196 |                |         |          | firmware from the host.                |
197 +----------------+---------+----------+----------------------------------------+
200 +----------------+---------+----------+----------------------------------------+
201 | QAIC_SSR       | 6 & 7   | AMSS     | Used to notify the host of subsystem   |
204 +----------------+---------+----------+----------------------------------------+
206 +----------------+---------+----------+----------------------------------------+
209 |                |         |          | channel between host and QSM for       |
211 +----------------+---------+----------+----------------------------------------+
213 |                |         |          | the host.                              |
214 +----------------+---------+----------+----------------------------------------+
215 | QAIC_STATUS    | 14 & 15 | AMSS     | Used to notify the host of Reliability,|
218 +----------------+---------+----------+----------------------------------------+
221 +----------------+---------+----------+----------------------------------------+
223 +----------------+---------+----------+----------------------------------------+
225 |                |         |          | device side logs with the host time    |
227 +----------------+---------+----------+----------------------------------------+
230 |                |         |          | the host time source.                  |
231 +----------------+---------+----------+----------------------------------------+
237 --------
239 The DMA Bridge is one of the main interfaces to the host from the device
250 * Request FIFO head pointer (offset 0x0). Read only by the host. Indicates the
252 * Request FIFO tail pointer (offset 0x4). Read/write by the host. Host
254 * Response FIFO head pointer (offset 0x8). Read/write by the host. Indicates
255   the latest item in the FIFO the host has consumed.
256 * Response FIFO tail pointer (offset 0xc). Read only by the host. Device
263 DBC registers are exposed to the host via the second BAR. Each DBC consumes
266 The actual FIFOs are backed by host memory. When sending a request to the QSM
267 to activate a network, the host must donate memory to be used for the FIFOs.
274 ------------
278 .. code-block:: c
343 	* Bits(1:0) contain the encoding of the doorbell length. 0 is 32-bit,
344 	  1 is 16-bit, 2 is 8-bit, 3 is reserved. The doorbell address
348 	data to write to the doorbell. Only the bits corresponding to
355 	* Bit(30) is the to-device DMA fence. Block this request until all
356 	  to-device DMA transfers are complete.
357 	* Bit(29) is the from-device DMA fence. Block this request until all
358 	  from-device DMA transfers are complete.
369 	  presync, which gates the DMA transfer. Only one presync is
384 the data pipeline can be synchronized such that the host can queue multiple
385 requests of data for the workload to process, but the DMA Bridge will only copy
390 -------------
395 .. code-block:: c
406 	status of this request. 0 is success. Non-zero is an error.
408 The DMA Bridge will generate a MSI to the host as a reaction to activity in the
410 algorithm, where it will only generate a MSI when the response FIFO transitions
411 from empty to non-empty (unless force MSI is enabled and triggered). In
412 response to this MSI, the host is expected to drain the response FIFO, and must
419 The NNC protocol is how the host makes requests to the QSM to manage workloads.
427 aligned. Since there are 64-bit elements in some NNC messages, 64-bit alignment
431 at most 4K in size from QSM to the host. From the host to the QSM, a message
437 ------------------------
449 	Activate a workload onto NSPs. The host must provide memory to be
487 If a particular workload crashes, QSM notifies the host via the QAIC_SSR MHI
489 multi-stage recovery process is then used to cleanup both sides, and get the
494 remain in on-card DDR, but the host will need to re-activate the workload if
513 some cases, to allow the host to control them. Examples include thermal limits,