Lines Matching refs:FPGA

13 		wrong during FPGA programming (something that the driver can't
18 		This is a superset of FPGA states and fpga manager driver
20 		to get the FPGA into a known operating state.  It's a sequence,
21 		though some steps may get skipped.  Valid FPGA states will vary
25 		* power off		= FPGA power is off
26 		* power up		= FPGA reports power is up
27 		* reset			= FPGA held in reset state
30 		* write init		= preparing FPGA for programming
31 		* write init error	= Error while preparing FPGA for programming
32 		* write			= FPGA ready to receive image data
36 		* operating		= FPGA is programmed and operating
43 		If FPGA programming operation fails, it could be caused by crc
45 		interface is to provide more detailed information for FPGA