65787820 | 28-Aug-2023 |
Vivek <quic_vchettri@quicinc.com> |
Revert "qcacmn: Increase the CE1 ring size to 1280 for Waikiki"
This reverts commit I794522751deb9a60e6487e42df48f582a5e01d2e.
Reason for revert: Changes for the fix is implemented as a different F
Revert "qcacmn: Increase the CE1 ring size to 1280 for Waikiki"
This reverts commit I794522751deb9a60e6487e42df48f582a5e01d2e.
Reason for revert: Changes for the fix is implemented as a different FR
Change-Id: I19f6e4362ed406c9906e333c1ee0bfa2fe14677e CRs-Fixed: 3598130
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ba534849 | 16-Aug-2023 |
Azmath Mohammed <quic_azmamoha@quicinc.com> |
qcacmn: Add ce_count check to avoid any buffer overflow
Add ce_count check to avoid any buffer overflow of "scn->ce_id_to_state" and "hif_state->pipe_info"
Change-Id: I77f074f631a86cb96badab27e6850
qcacmn: Add ce_count check to avoid any buffer overflow
Add ce_count check to avoid any buffer overflow of "scn->ce_id_to_state" and "hif_state->pipe_info"
Change-Id: I77f074f631a86cb96badab27e6850e0969331dba CRs-Fixed: 3589967
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5040e12d | 18-Aug-2023 |
Yu Tian <quic_yutian@quicinc.com> |
qcacmn: call fw diag drain before complete ce tasks
FW diag drain may wake up delay reg write WQ, and this happens after ce tasks completion check. Change is to make FW diag drain operation before c
qcacmn: call fw diag drain before complete ce tasks
FW diag drain may wake up delay reg write WQ, and this happens after ce tasks completion check. Change is to make FW diag drain operation before complete check.
Change-Id: I209c88cc5c2d5cb3b3195d1ae08b4c0c29903fa5 CRs-Fixed: 3591738
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a641238d | 14-Aug-2023 |
Venkateswara Naralasetty <quic_vnaralas@quicinc.com> |
qcacmn: Enable wlan datapath CE IRQ affine
Set affinity to assign WLAN CE datapath IRQs to perf clusters based on the INI config.
Change-Id: I63f96bc6b434af2e322ef277096e5547cfa6835a CRs-Fixed: 359
qcacmn: Enable wlan datapath CE IRQ affine
Set affinity to assign WLAN CE datapath IRQs to perf clusters based on the INI config.
Change-Id: I63f96bc6b434af2e322ef277096e5547cfa6835a CRs-Fixed: 3590583
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8aa32229 | 09-Aug-2023 |
Karthik Kantamneni <quic_vkantamn@quicinc.com> |
qcacmn: Enhance latest HIF CE event history
Latest CE event history is helpful to analyze CE reaping issues when dump is not available. Enhance latest HIF CE event history to capture last two events
qcacmn: Enhance latest HIF CE event history
Latest CE event history is helpful to analyze CE reaping issues when dump is not available. Enhance latest HIF CE event history to capture last two events, so that during error situations more data is available to detect CE reaping issues.
Change-Id: I503ec5c84ff02b967e1ce93954725ffd9866e93c CRs-Fixed: 3590596
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38997d77 | 16-Aug-2023 |
Amit Mehta <quic_amitmeht@quicinc.com> |
qcacmn: Fix format specifier for macro which uses BIT()
BIT() is unsigned long int, and is being printed using an incorrect format specifier. This leads to a compilation failure.
Fix the format spe
qcacmn: Fix format specifier for macro which uses BIT()
BIT() is unsigned long int, and is being printed using an incorrect format specifier. This leads to a compilation failure.
Fix the format specifier for macro which uses BIT(). also typecast the macro to unsigned long for CONFIG_SLUB_DEBUG_ON case where IS_CE_DEBUG_ONLY_FOR_CRIT_CE is of type unsigned int.
Change-Id: I5a717fd45c80b8245522c895c36aaafd46592454 CRs-Fixed: 3591809
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2c0fb4ff | 10-Aug-2023 |
Amit Mehta <quic_amitmeht@quicinc.com> |
qcacmn: Set enable_rpm earlier in hdd_wlan_start_modules
Currently enable_rpm is being set in hif_rtpm_start which is called later in hdd_wlan_start_modules, this can result in race between hif_rtpm
qcacmn: Set enable_rpm earlier in hdd_wlan_start_modules
Currently enable_rpm is being set in hif_rtpm_start which is called later in hdd_wlan_start_modules, this can result in race between hif_rtpm_start and hif_rtpm_put.
To fix the issue set enable_rpm earlier to avoid race condition.
Change-Id: Iaa4ffda4eef3050f43ff5ca2bdba555abb8a0b47 CRs-Fixed: 3581962
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bb3b7986 | 09-Aug-2023 |
Manikanta Pubbisetty <quic_mpubbise@quicinc.com> |
qcacmn: Fix compilation issues with NAPI stats on WCN6450
Fix compilation issues with NAPI stats on WCN6450
Change-Id: I0339a510c715009255bc00841d44bd06357b252b CRs-Fixed: 3583455 |
63979604 | 08-Aug-2023 |
Amit Mehta <quic_amitmeht@quicinc.com> |
qcacmn: Add memory barrier to avoid inconsistent read for valid flag
Currently there is no memory barrier after valid flag read, which can result in reading q_elem values in random order, due to whi
qcacmn: Add memory barrier to avoid inconsistent read for valid flag
Currently there is no memory barrier after valid flag read, which can result in reading q_elem values in random order, due to which host can read stale entried from the q_elem.
To fix the issue add memory barrier to avoid inconsistent read for valid flag.
Change-Id: I9431d4f62188def37c2515e376a28f3985733f85 CRs-Fixed: 3577746
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3ac14805 | 03-Aug-2023 |
Manikanta Pubbisetty <quic_mpubbise@quicinc.com> |
qcacmn: Fix issue with IRQ re-enablement for CE IRQs
Currently on WCN6450 which is based on IPCI, there is a problem in re-enabling the IRQs while firmware recovery is in progress.
While processing
qcacmn: Fix issue with IRQ re-enablement for CE IRQs
Currently on WCN6450 which is based on IPCI, there is a problem in re-enabling the IRQs while firmware recovery is in progress.
While processing the CE IRQs, if there’s an active recovery happening in the host (due to FW assert), we are leaving the IRQs disabled in the kernel.
Fix this by refactoring the code such that hif_irq_disable() is called only when there is no active recovery.
Change-Id: I4e3ccbb5f820645597feb724ddfe321e7d7d1a5f CRs-Fixed: 3579429
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5748e165 | 02-Aug-2023 |
Amit Mehta <quic_amitmeht@quicinc.com> |
qcacmn: Change log level for hal_info and hif_info
Currently hal_info and hif_info logs levels are set to QDF_TRACE_LEVEL_INFO, which results in prints being logged to dmesg buffer.
To prevent prin
qcacmn: Change log level for hal_info and hif_info
Currently hal_info and hif_info logs levels are set to QDF_TRACE_LEVEL_INFO, which results in prints being logged to dmesg buffer.
To prevent prints logging into dmesg buffer, changes logging level to QDF_TRACE_LEVEL_INFO_HIGH.
Change-Id: I039c5e7b6b47f1ffda8e32ff44322d1963648c41 CRs-Fixed: 3577831
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bb613945 | 31-Jul-2023 |
Karthik Kantamneni <quic_vkantamn@quicinc.com> |
qcacmn: Fix accessing unused CE channel ctrl register in WCN6450
Currently host is programming IDX_UPD_EN for all the CE channels even though which are not used by host.
Fix this by programming CE
qcacmn: Fix accessing unused CE channel ctrl register in WCN6450
Currently host is programming IDX_UPD_EN for all the CE channels even though which are not used by host.
Fix this by programming CE ctrl register which are used by host.
Change-Id: Ic0c133d87c688257ef2047bcb177228e25369aed CRs-Fixed: 3575870
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26eceff0 | 16-May-2023 |
Jeff Johnson <quic_jjohnson@quicinc.com> |
qcacmn: Fix hif_cleanup_static_buf_to_target() typo
Function hif_cleanup_static_buf_to_target() has multiple implementations, with one chosen by conditional compilation. The version where CONFIG_BYP
qcacmn: Fix hif_cleanup_static_buf_to_target() typo
Function hif_cleanup_static_buf_to_target() has multiple implementations, with one chosen by conditional compilation. The version where CONFIG_BYPASS_QMI is defined and QCN7605_SUPPORT is not defined has a typo (snc instead of scn), so fix it.
Change-Id: Ifbfee8cb53e987216b46507e336bf3aa3de7bf6c CRs-Fixed: 3500203
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f243b447 | 17-Jul-2023 |
Karthik Kantamneni <quic_vkantamn@quicinc.com> |
qcacmn: Fix Runtime PM resume issue for ipci interface
For ipci interface platforms, currently RTPM resume is requested from CE interrupt handler even when suspend is in progress. But ideally we sho
qcacmn: Fix Runtime PM resume issue for ipci interface
For ipci interface platforms, currently RTPM resume is requested from CE interrupt handler even when suspend is in progress. But ideally we should request resume only RTPM state is in suspended, since as part of suspend sequence also we will get CE WOW events and this should not trigger resume.
Fix this by requesting resume from CE interrupt handler only when driver state is suspended.
Change-Id: I450d6c48809afae26fe863184766ab5141d25691 CRs-Fixed: 3554857
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b965b762 | 13-Jul-2023 |
Karthik Kantamneni <quic_vkantamn@quicinc.com> |
qcacmn: Fix race with F.W in updating CE control register
In current case when RRI on DDR feature is enabled then host programs CE control register, but there is chance of F.W also programming the C
qcacmn: Fix race with F.W in updating CE control register
In current case when RRI on DDR feature is enabled then host programs CE control register, but there is chance of F.W also programming the CE control register around same time this leads to race and chance of either host/F.W value getting over written.
So to avoid this while programming the CE control register for RRI on DDR enablement, update it with F.W programming value also i.e DMA length. So if incase register value over written due to race proper value will be updated to register either by host/F.W.
Change-Id: I2560c74726b21128d1cd50805d987fda1b2a1230 CRs-Fixed: 3561689
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77094355 | 17-Apr-2023 |
Zhiwei Yang <quic_zhiwyang@quicinc.com> |
qcacmn: add hif_event_desc_history to ssr driver dump
Current code doesn't have hif_event_desc_history in ssr driver dump. Fix this by adding hif_event_desc_history and hif_event_hist_max to the ssr
qcacmn: add hif_event_desc_history to ssr driver dump
Current code doesn't have hif_event_desc_history in ssr driver dump. Fix this by adding hif_event_desc_history and hif_event_hist_max to the ssr driver dump regions.
And add more parameters for parsing hif_ce_desc_history_buff.
Change-Id: I02cbfc7b9ea0c53d31ad351377d4644f1ad189d1 CRs-Fixed: 3469140
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94c56062 | 10-Jul-2023 |
Manikanta Pubbisetty <quic_mpubbise@quicinc.com> |
qcacmn: Reduce size of T2H HTT CE pipe for WCN6750
Currently, the size of target to host CE pipe for HTT RX communication for WCN6750 is 512. The data that we receive on this pipe is not very freque
qcacmn: Reduce size of T2H HTT CE pipe for WCN6750
Currently, the size of target to host CE pipe for HTT RX communication for WCN6750 is 512. The data that we receive on this pipe is not very frequent and hence 512 entries are not needed.
Reduce the size of the HTT RX ring for WCN6750. This will also bring down the memory requirement for this ring considerably.
Change-Id: I690fa34c76b1b683a1518964088bc7540ca751a4 CRs-Fixed: 3554428
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6e25e7d3 | 23-Mar-2023 |
Madhavan Ganesan <quic_madhgane@quicinc.com> |
qcacmn: Fill BAR address for IPQ5332, QCN6122 and QCA5018 chipset
Update the BAR address to plat_priv for IPQ5332, QCA5018 and QCN6122.
CRs-Fixed: 3198433 Change-Id: I5e22ebcdb6b42474bdc8e8f89ff66e
qcacmn: Fill BAR address for IPQ5332, QCN6122 and QCA5018 chipset
Update the BAR address to plat_priv for IPQ5332, QCA5018 and QCN6122.
CRs-Fixed: 3198433 Change-Id: I5e22ebcdb6b42474bdc8e8f89ff66e0775b00958
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cbe81707 | 15-Jun-2023 |
Manikanta Pubbisetty <quic_mpubbise@quicinc.com> |
qcacmn: Add HIF CE RX support to WBUFF
Currently, WBUFF is being used only for WMI TX buffers. Add HIF CE RX buffers support to WBUFF in an effort to re-use the copy engine RX buffers instead of fre
qcacmn: Add HIF CE RX support to WBUFF
Currently, WBUFF is being used only for WMI TX buffers. Add HIF CE RX buffers support to WBUFF in an effort to re-use the copy engine RX buffers instead of freeing/allocating buffers for every CE RX transaction. This fixes the problem of CE RX memory fragmentation.
Change-Id: Id9c043a5c5d0882a7994fa03cd8c335555d46b8d CRs-Fixed: 3534539
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147467b9 | 07-Jul-2023 |
SACHIN AHUJA <quic_sahuja@quicinc.com> |
qcacmn: Add the SOCID for WCN6750_V2 chip
SOC ID is missing for WCN6750_V2 and as a result correct string for chip is not sent to CNE. This leads to the issue in Wifi calls.
Add the SOC ID for WCN6
qcacmn: Add the SOCID for WCN6750_V2 chip
SOC ID is missing for WCN6750_V2 and as a result correct string for chip is not sent to CNE. This leads to the issue in Wifi calls.
Add the SOC ID for WCN6750_V2.
CRs-Fixed: 3552566 Change-Id: I80d19742f6ffa1c5b03f1f2576c6e4c0c4a1c1db
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51ddb93d | 11-Jul-2023 |
Venkateswara Naralasetty <quic_vnaralas@quicinc.com> |
qcacmn: add periodic and host Tx/Rx stats support for WCN6450
Changes required to support periodic and host Tx/Rx stats for WCN6450.
Command to request and dump the host Tx/Rx stats, iwpriv wlan0 t
qcacmn: add periodic and host Tx/Rx stats support for WCN6450
Changes required to support periodic and host Tx/Rx stats for WCN6450.
Command to request and dump the host Tx/Rx stats, iwpriv wlan0 txrx_stats <stats no> <mac_id> mac_id: 0 - mac0(5 GHz), 1 - mac1(2 GHz) 0 for single mac stats no: 20 - TXRX_CLEAR_STATS 21 - TXRX_RX_RATE_STATS 22 - TXRX_TX_RATE_STATS 23 - TXRX_TX_HOST_STATS 24 - TXRX_RX_HOST_STATS 25 - TXRX_AST_STATS 26 - TXRX_SRNG_PTR_STATS 27 - TXRX_RX_MON_STATS 29 - TXRX_SOC_CFG_PARAMS 30 - TXRX_PDEV_CFG_PARAMS 31 - TXRX_NAPI_STATS 32 - TXRX_SOC_INTERRUPT_STATS 33 - TXRX_SOC_FSE_STATS
Change-Id: Ibda4d531c9074a24f8c39916b44d9e3c38f189ee CRs-Fixed: 3485279
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fc93f83a | 26-Jun-2023 |
Venkateswara Naralasetty <quic_vnaralas@quicinc.com> |
qcacmn: Add SWLM support for WCN6450
Changes required to support SWLM feature on wcn6450.
Change-Id: I306cba8dcefa8f34a9546285b33b974987aec625 CRs-Fixed: 3540269 |
6ca74c40 | 07-Jul-2023 |
Nandha Kishore Easwaran <quic_nandhaki@quicinc.com> |
qcacmn: Add alignment of 4 bytes back
This reverts commit Ib680547d2bcfe57b6eadda5301677d68e4a931a4
Change-Id: Iffc7f2cdab2d1015db4b3f0dfc0ea697e0388238 CRs-Fixed: 3552537 |
a3a5a72b | 01-Jun-2023 |
Venkateswara Naralasetty <quic_vnaralas@quicinc.com> |
qcacmn: Add delayed reg write support for wcn6450
Current HAL delayed reg write is tied to SRNG notions, hence implement delayed reg write logic in HIF since WCN6450 does not use SRNG interface.
Ne
qcacmn: Add delayed reg write support for wcn6450
Current HAL delayed reg write is tied to SRNG notions, hence implement delayed reg write logic in HIF since WCN6450 does not use SRNG interface.
New feature flag FEATURE_HIF_DELAYED_REG_WRITE is introduced to disable/enable this support.
Change-Id: Id7087ad53cd5879cf49ee0e84dd727de61137541 CRs-Fixed: 3519702
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7f998d62 | 04-Jul-2023 |
Li Feng <quic_lifeng@quicinc.com> |
qcacmn: Bypass hif apps irqs handle for single MSI case
Regarding to the platform suspend, generally the hif_bus_suspend() will disable the CE irqs, however the irq is shared in the single MSI case,
qcacmn: Bypass hif apps irqs handle for single MSI case
Regarding to the platform suspend, generally the hif_bus_suspend() will disable the CE irqs, however the irq is shared in the single MSI case, so the MHI irq is disabled as well which cause no MHI ring event notified in the following pci bus suspend.
The fix is to bypass hif apps irqs handle for single MSI case during suspend-resume stage.
Change-Id: I4f9068900e85fe57c2a82d841846b3fff6da0696 CRs-Fixed: 3549884
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